Specifications

130 Product Errata
41322 Rev. 3.84 August 2011
Revision Guide for AMD Family 10h Processors
420 Instruction-Based Sampling Engine May Generate Interrupt
that Cannot Be Cleared
Description
A micro-op that is tagged by the Instruction-Based Sampling (IBS) execution engine shortly before
the software clears the IBS Execution Control Register[IbsOpEn] (MSRC001_1033[17]) may create
a condition in which the IBS sampling engine continuously generates an interrupt. This condition can
exist even if IBS is not re-enabled.
Potential Effect on System
Processor core may not make forward progress, usually resulting in a system crash or hang.
Suggested Workaround
To disable the IBS execution sampling engine, software should first clear IbsOpMaxCnt to 0000h
without changing IbsOpEn (write MSRC001_1033 to 00000000_00020000h). After IbsOpMaxCnt is
set to zero, software should then perform a second write to clear IbsOpEn.
Fix Planned
No