Specifications

124 Product Errata
41322 Rev. 3.84 August 2011
Revision Guide for AMD Family 10h Processors
414 Processor May Send Mode Register Set Commands to DDR3
DIMM Incorrectly
Description
The processor may send a Mode Register Set (MRS) command to a DDR3 DIMM without satisfying
the auto-refresh row cycle time programmed at the DRAM Timing High Register F2x[1, 0]8C. In
addition, the processor may send an MRS command to a DDR3 DIMM that has an active bank. This
erratum applies only when DRAM Configuration High Register F2x[1, 0]94[15] (PowerDownEn) is
programmed to 1b, F2x[1, 0]94[Ddr3Mode] is programmed to 1b, and DRAM MRS Register F2x[1,
0]84[23] (PchgPDModeSel) is programmed to 1b.
Potential Effect on System
For systems without ECC, undefined system behavior that usually results in a system hang. Systems
with ECC enabled may experience repeated multiple-bit ECC errors.
Suggested Workaround
System software should program F2x[1, 0]84[23] (PchgPDModeSel) to 0b.
Fix Planned
No