Specifications

118 Product Errata
41322 Rev. 3.84 August 2011
Revision Guide for AMD Family 10h Processors
400 APIC Timer Interrupt Does Not Occur in Processor C-States
Description
An APIC timer interrupt that becomes pending in low-power states C1E or C3 will not cause the
processor to enter the C0 state even if the interrupt is enabled by Timer Local Vector Table
Entry[Mask], APIC320[16]). APIC timer functionality is otherwise unaffected.
Potential Effect on System
System hang may occur provided that the operating system has not configured another interrupt
source.
APIC timer interrupts may be delayed or, when the APIC timer is configured in rollover mode
(APIC320[17]), the APIC timer may roll over multiple times in the low-power state with only one
interrupt presented after the processor resumes. The standard use of the APIC timer does not make
this effect significant.
Suggested Workaround
Operating system software should enable another source of timer interrupts, such as the High
Precision Event Timer, before it enters the C1 state by executing the HLT instruction and C1E is
enabled using Interrupt Pending and CMP-Halt Register[C1eOnCmpHalt or SmiOnCmpHalt]
(MSRC001_0055[28:27] are not 00b). For purposes of determining if C1E is enabled, the operating
system should not sample MSRC001_0055 until after ACPI has been enabled.
Operating system software should enable another source of timer interrupts, such as the High
Precision Event Timer, when the processor enters the C3 state.
It is possible for the system to implement a hardware fix to C1E mode on some processor revisions
and some packages. This is indicated by OSVW[1] and no workaround is necessary when
OSVW_Length >= 2 and OSVW[1] is zero. Due to erratum #669, a similar workaround may be
required even when OSVW[1] = 0b. An operating system workaround for C3 mode is always
necessary, regardless of the setting of OSVW[1].
Fix Planned
C1E state: Yes
C3 state: No