Specifications

Product Errata 117
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
399 Memory Clear Initialization May Not Complete if DCT0 Fails
Training
Description
During DRAM initialization, memory clearing that is initiated by writing 1b to DRAM Controller
Select Low Register F2x110[3] (MemClrInit) may fail to complete when all of the following
conditions are true:
• All DRAM connected to DCT0 is disabled by system software as a result of a DRAM training
failure.
• DRAM connected to DCT1 is successfully trained and enabled by system software.
• DRAM Base System Address Register F1x120[20:0] (DramBaseAddr) is not programmed to 0
when MemClrInit is programmed to 1b.
Potential Effect on System
If DramBaseAddr is greater than or equal to the total DRAM size on DCT1 and the erratum
conditions are satisfied, the system may fail to boot.
If DramBaseAddr is less than the total DRAM size on DCT1 and the erratum conditions are satisfied,
memory clear initialization will not clear all memory locations on DCT1. If ECC is enabled, this may
result in unexpected ECC errors occurring on uninitialized memory.
Suggested Workaround
No workaround required if system software skips memory clear initialization and does not use
memory on a node when any memory training errors have been reported on that node.
System software developers that wish to use memory clear initialization regardless of memory
training error status should program DramBaseAddr to 0 before programming MemClrInit to 1b.
After completion of memory clear initialization, system software should restore the original value of
DramBaseAddr.
Fix Planned
No