Specifications

Product Errata 109
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
388 L3 Cache Scrubbing Does Not Bypass Disabled L3 Cache
Locations
Description
The processor does not discontinue scrubbing L3 cache locations that are disabled using the L3 Cache
Index Disable Registers F3x[1C0, 1BC].
Potential Effect on System
ECC errors that occur when scrubbing disabled L3 cache locations can generate unexpected machine
check exceptions.
Suggested Workaround
System software should program Scrub Rate Control Register F3x58[28:24] (L3Scrub) to 00000b
before disabling any L3 cache locations. This workaround should not be applied when all L3 cache
locations are enabled.
Fix Planned
Yes