Specifications

104 Product Errata

41322 Rev. 3.84 August 2011

Revision Guide for AMD Family 10h Processors

383 CPU Core May Machine Check When System Software

Changes Page Tables Dynamically

Description

If system software performs uncommon methods to change the page size of an active page table that

is valid, the CPU core may, under a highly specific and detailed set of conditions, form duplicate TLB

entries for a single linear address. The CPU core will machine check if this page is then accessed prior

to it being invalidated from the TLB.

Potential Effect on System

Uncorrectable machine check exception for an L1 TLB Multimatch error. The MC0_STATUS

or may not be set.

Suggested Workaround

Affected software must ensure that page sizes are only increased or decreased after the entry is

invalidated and flushed out of all TLBs. When flushing multiple entries from the TLB, software may

wish to use a single MOV CR3 value to invalidate the TLB instead of repetitive INVLPG

instructions.

Additionally, hypervisors should ensure that the effects of a nested paging guest that exposes the

condition is limited to the guest virtual machine with the following steps:

1. During hypervisor initialization, the hypervisor should set MSRC001_1022[47].

2. The hypervisor should intercept machine-check exceptions (#MC) by setting VMCB offset 08h

bit 12h.

3. When a VM_EXIT occurs with exit code 52h, the hypervisor must perform all the functions of a

#MC exception handler. At a minimum, the hypervisor must clear MCi_STATUS registers and

clear MCG_STAT[MCIP] (MSR0000_017A[2]). Failure to do so will result in a system shutdown

in the event of a second machine check.

4. During the above process, the hypervisor should inspect the contents of MSR0000_0401 for the

exact signature described in the Potential Effect on System. If the signature exists, then the

hypervisor should abort the guest.

5. The hypervisor should flush the TLB.

6. The hypervisor should then resume operation.

Fix Planned