Specifications

Product Errata 103
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
382 L3 Cache Index Disable Cannot Be Modified After L3 Cache is
Enabled
Description
The processor does not support the disabling of L3 indices using the L3 Cache Index Disable
Registers (F3x[1C0, 1BC]) after the cache subsystem has been enabled (CR0[CD] = 0b).
Potential Effect on System
If software modifies F3x[1C0, 1BC] after the L3 cache has been enabled using CR0[CD],
unpredictable system behavior may result.
Suggested Workaround
None.
Fix Planned
Yes