Specifications

100 Product Errata
41322 Rev. 3.84 August 2011
Revision Guide for AMD Family 10h Processors
374 Processor Read From L3 Cache May Return Stale Data
Description
Under highly specific and detailed internal timing conditions, a processor read from the L3 cache may
return stale data.
Potential Effect on System
Unpredictable system behavior due to incorrect read data.
Suggested Workaround
System software should set F3x1B8[18] to 1b.
Fix Planned
Yes