Specifications

46837 Rev. 1.0 March 2010

SB700 Family Product Errata

Product Errata

3 Support for SPI ROM Greater Than 1 MB

Description

An issue has been identified with address mapping for SPI flash ROMs greater than 1 MByte (8 MBits) size.

Due to an incorrect implementation of address mapping logic in the Southbridge SPI ROM controller, the

ROM access to the top of ROM area using real mode addressing (e.g., 0xF000 segment) will not be

translated to the correct physical address in the ROM. When accessing the top of ROM using real mode

addressing, the SPI ROM controller will always return the data from the first 1 MB address space of the SPI

ROM. If the ROM size is 1 MB, then the correct data will be returned, however, for any ROM size greater

than 1 MB, the SPI ROM controller will still return data from first 1 MB area instead of returning data from

the top of ROM address space.

Potential Effect on System

When SPI flash ROM parts that are greater than 1 MB in capacity are used, the system may hang

during BIOS post. This SPI ROM issue is not applicable to the following system configurations:

1. The system is using EFI BIOS code structure.

2. The SPI Flash ROM is not connected directly to the Southbridge SPI ROM interface but

instead connected to the LPC SIO or LPC EC and the Southbridge is configured for LPC

ROM configuration.

EFI BIOS switches to the protected mode right after the CPU jumps to the reset vector. In protected

mode, EFI executes code and accesses data in the top of 4 GB space when doing ROM access, which

doesn’t behave like a traditional BIOS which is running code below 1 MB.

Suggested Workaround

The BIOS boot code which is normally located at the top of the BIOS ROM should be duplicated on top

of 1 MB address space. The normal BIOS code execution should be modified to jump over the boot

code when crossing the 1 MB address boundary.

Fix Planned

This issue is resolved in SB710/SB750 revision A14.