Specifications

SB700 Family Product Errata
46837 Rev. 1.0 March 2010
4
Product Errata
Product Errata Summary
Except where otherwise noted, this product errata is applicable to SB700, SB710 and SB750.
A unique errata reference number (ERN) has been assigned to each erratum within this document for user
convenience in tracking the errata within specific revision levels. Table 1 cross-references the revisions of the
part to each erratum. An “X” indicates that the erratum applies to the revision. The absence of an “X”
indicates that the erratum does not apply to the revision. An “*” indicates advance information that the
erratum has been fixed but not yet verified. “No fix planned” indicates that no fix is planned for current or
future revisions of the ASIC.
Table 1: Cross-Reference of Product Revision to Errata
# Errata Description
ASIC Revision
SB700
A12
SB710/SB750
A14
3 Support for SPI ROM Greater Than 1 MB X
4 SYS_RESET# Signal Does Not Disable the Interrupt Controller X
5 System Time Lag / Performance Counter Lag When Spread Spectrum is Enabled X
7 Resume From S3 State with USB 1.1 Device Behind USB 2.0 HUB X
8 USB 1.1 ISO OUT Devices May Not Function Properly X
9 USB 2.0 Card Reader Devices May Not Function Properly No Fix Planned
10 CRC Error on TX Link During Hibernation X
11 Enabling EHCI Dynamic Clock Gating May Cause Bug Code 0xFE System Error No Fix Planned
13 SMBUS May Write Corrupted Data to Slave Device X
15
USB Devices Cannot be Detected or Will Not Function When the EHCI Advanced
Periodic Descriptor Cache Feature is Enabled
X
16 Internal Pull-Up on the EC GPIO8 Pin May Cause Leakage X
17 USB ISO IN Devices May Not Function Properly No Fix Planned
18 System May Not Enter or Resume from S5 After an Unconditional Power Down No Fix Planned
19 Non-Posted Writes Using 64-bit Addressing for SKINIT Instructions No Fix Planned
20 A-Link Deadlock No Fix Planned
21 SMI Re-ordering No Fix Planned
22
Transmission Errors on Packet Identifier May Cause USB Host Controller To
Reinitialize Device
No Fix Planned
23 USB Wake on Connect/Disconnect with Low Speed Devices No Fix Planned
24
Corrupted Interrupt Vector when both IOAPIC and PIC Controllers Process
Interrupts from the Same Source
No Fix Planned
25 S-state Failures when Message-Triggered C1e is Enabled No Fix Planned
26 Excessive Latencies May Cause Overwritten USB OHCI Controller Request No Fix Planned
27 Misinterpreted MSI Requests May Result in Corrupted LPC DMA Data No Fix Planned
30 Nmi_Enable is Altered When Writing to IO_Reg:72h No Fix Planned
31 Indeterminate Boot Up State of RTC Bank Selection Bit (DV0) No Fix Planned