SB700 Family Product Errata Silicon Errata for SB700, SB710 and SB750 Publication # 46837 Revision: 1.
© 2010 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice.
46837 Rev. 1.0 March 2010 SB700 Family Product Errata Revision History Date Revision March 2010 1.0 Description • Initial public release based on OEM version 1.
6837 SB700 Family Product Errata Rev. 1.0 March 2010 Product Errata Summary Except where otherwise noted, this product errata is applicable to SB700, SB710 and SB750. A unique errata reference number (ERN) has been assigned to each erratum within this document for user convenience in tracking the errata within specific revision levels. Table 1 cross-references the revisions of the part to each erratum. An “X” indicates that the erratum applies to the revision.
46837 Rev. 1.0 March 2010 SB700 Family Product Errata Product Errata 3 Support for SPI ROM Greater Than 1 MB Description An issue has been identified with address mapping for SPI flash ROMs greater than 1 MByte (8 MBits) size. Due to an incorrect implementation of address mapping logic in the Southbridge SPI ROM controller, the ROM access to the top of ROM area using real mode addressing (e.g., 0xF000 segment) will not be translated to the correct physical address in the ROM.
46837 SB700 Family Product Errata 4 Rev. 1.0 March 2010 SYS_RESET# Signal Does Not Disable the Interrupt Controller Description The SYS_RESET# signal is used to reset the Southbridge internal logic. This signal is normally connected to system reset button on the front panel in a desktop system. Due to an incorrect implementation of the SYS_RESET# logic, the interrupt controller and interrupt message generation logic is only reset by RSMRST#.
46837 Rev. 1.0 March 2010 5 System Time Lag / Performance Counter Lag When Spread Spectrum is Enabled SB700 Family Product Errata Description ® SRC_CLK of the external clock generator is a spread-capable PCIe 100 MHz clock which is used by an internal PLL of the SB7xx to generate a 14 MHz reference system clock.
46837 SB700 Family Product Errata 7 Rev. 1.0 March 2010 Resume From S3 State with USB 1.1 Device Behind USB 2.0 Hub Description On S3 resume, the USB host controller does not drive the resume signal within 100 µS as required. Some controllers used in USB hubs may not tolerate this resume timing violation and will have a problem in resuming correctly from the previous sleep state. Potential Effect on System On Windows Vista and Windows XP operating systems, if a USB 1.1 device is connected to a USB 2.
46837 Rev. 1.0 March 2010 8 USB 1.1 ISO OUT Devices May Not Function Properly SB700 Family Product Errata Description The audio from a USB 1.1 ISO out device (e.g., USB speakers) may be corrupted when both the A-Link power saving feature “PLL power down mode” and the L1 link power management feature are enabled. The PLL power down mode is a power saving feature that is optionally enabled for mobile systems.
46837 SB700 Family Product Errata 9 Rev. 1.0 March 2010 USB 2.0 Card Reader Devices May Not Function Properly Description An issue has been identified with USB 2.0 card reader devices that use SMSC controllers. With these devices, if the application is playing back video or audio from card reader media, the data transfer from the device to the host may get stalled.
46837 Rev. 1.0 March 2010 10 CRC Error on TX Link During Hibernation SB700 Family Product Errata Description A system error has been observed during extended S4 hibernation cycling using the MS PWRTST or other similar utility. The stop error message is triggered by a sequence of events that is initiated by a transmission error on the SATA link caused by a hardware logic bug in the SATA PHY.
46837 SB700 Family Product Errata 11 Rev. 1.0 March 2010 Enabling EHCI Dynamic Clock Gating May Cause Bug Code 0xFE System Error Description A system error has been observed during extended S4 Hibernation or Reboot cycling using the MS PWRTST or other similar utility. The arbiter in the Southbridge that controls the down stream memory traffic to the USB controller does not fully support the EHCI clock gating feature.
46837 Rev. 1.0 March 2010 13 SMBUS May Write Corrupted Data to Slave Device SB700 Family Product Errata Description On some platforms, the SMBUS may cause incorrect data to be written to the slave device. If the system design has non-ideal signal integrity on the SMBUS interface (possibly due to termination mismatch), then it is possible to encounter glitches on the interface due to reflections.
46837 SB700 Family Product Errata 15 Rev. 1.0 March 2010 USB Devices Cannot be Detected or Will Not Function When the EHCI Advanced Periodic Descriptor Cache Feature is Enabled Description Due to the logic implementation of the Advanced Periodic Descriptor Cache fetch logic, an end case scenario where a descriptor type may be decoded incorrectly or sometimes not decoded at all may result in a system hang. Potential Effect on System This issue has only been observed on Linux® platforms.
46837 Rev. 1.0 March 2010 16 Internal Pull-Up on the IMC GPIO8 Pin May Cause Leakage SB700 Family Product Errata Description If the internal pull-up on IMC GPIO8 pin is enabled, the I/O pad of this pin may have internal leakage causing voltage to be present on the pin. Potential Effect on System The leakage will not cause any functional problems on the south bridge but could potentially be an issue for devices that interface with it.
46837 SB700 Family Product Errata 17 Rev. 1.0 March 2010 USB ISO IN Devices May Not Function Properly Description Data from a USB ISO IN device (e.g., video data from a USB TV tuner) may be corrupted when both the ALink power savings feature “PLL power down mode” and the L1 link power management features are enabled. With both features enabled, the USB controller may encounter an increased delay in fetching the data from memory.
46837 Rev. 1.0 March 2010 18 System May Not Enter or Resume from S5 After an Unconditional Power Down SB700 Family Product Errata Description Platforms using any PCIe devices that do not support the PME_Turn_Off broadcast message protocol may experience an intermittent system hang during repeated power cycle testing.
46837 SB700 Family Product Errata 19 Rev. 1.0 March 2010 Non-Posted Writes Using 64-bit Addressing for SKINIT Instructions Description Data corruption may occur when 64-bit non-posted write cycles are sent to the Southbridge during the use of SKINIT (Security Kernel Initialization) instructions. Potential Effect on System Systems that require the use of SKINIT to support TPM-related security features may not function properly.
46837 Rev. 1.0 March 2010 20 A-Link Deadlock SB700 Family Product Errata Description Under a highly specific and detailed set of stress conditions, including unusually high DMA read and write traffic and host-initiated traffic, a downstream posted or non-posted write may result in a deadlock condition.
46837 SB700 Family Product Errata 21 Rev. 1.0 March 2010 SMI Re-ordering Description Under a highly specific and detailed set of conditions including unusually high artificially-throttled DMA traffic, the response for an IO write to the SMI command port can pass the upstream SMI, thereby violating an ordering requirement. As a result, SMI interrupt service routines that require the interrupt be taken on the instruction boundary following the IO write to the SMI command port may not function properly.
46837 Rev. 1.0 March 2010 22 Transmission Errors on Packet Identifier May Cause USB Host Controller To Reinitialize Device SB700 Family Product Errata Description When receiving a packet identifier (PID) from a USB device while performing asynchronous data transfers, the USB host controller may not compare the packet type field to its check bits if the incoming packet type decodes as a STALL handshake.
46837 SB700 Family Product Errata 23 Rev. 1.0 March 2010 USB Wake on Connect/Disconnect with Low Speed Devices Description Due to an incorrect implementation in the USB logic, the EHCI controller is not able to detect the connection/disconnection of low speed USB 1.1 devices. If the low speed device is not detected, the internal ACPI logic will not be informed that a PME needs to be generated to wake the system when USB device is connected.
46837 Rev. 1.0 March 2010 24 Corrupted Interrupt Vector when both IOAPIC and PIC Controllers Process Interrupts from the Same Source SB700 Family Product Errata Description Interrupts from the same source initiated from both the IOAPIC and PIC controllers will result in a corrupted interrupt vector. Potential Effect on System The manifestation of this issue will be dependent on the hypervisor or operating system and be limited to intermittent error messages that refer to an APIC illegal vector.
46837 SB700 Family Product Errata 25 Rev. 1.0 March 2010 S-state Failures when Message-Triggered C1e is Enabled Description An S-state entry cycle will fail to complete if it was preceded by a message-triggered C1e cycle. Potential Effect on System When message-triggered C1e is enabled, a system hang (with no screen display) will occur when the system enters a sleep state. This failure has only been observed when using the S1 sleep state.
46837 Rev. 1.0 March 2010 26 Excessive Latencies May Cause Overwritten USB OHCI Controller Request SB700 Family Product Errata Description Requests from USB OHCI controllers may be overwritten if the latency for any pending request by the USB controller is very long (in the range of milliseconds). Potential Effect on System An operating system crash may occur as a result of USB 1.1 devices becoming unresponsive.
46837 SB700 Family Product Errata 27 Rev. 1.0 March 2010 Misinterpreted MSI Requests May Result in Corrupted LPC DMA Data Description An LPC device that supports DMA may encounter data corruption if used with an operating system that supports HPET MSI (e.g., Windows 7). This is due to a logic bug in the LPC controller that may cause pending MSI requests to be interpreted as a DMA cycle.
46837 Rev. 1.0 March 2010 30 Nmi_Enable is Altered When Writing to IO_Reg:72h SB700 Family Product Errata Description A write to IO_Reg:72h (Alternate RTC address) may alter bit 7 (NMI_ENABLE) of IO_Reg:70h. The altered value for IO_Reg:70h[7] is not necessarily related to the value being written into IO_Reg:72h[7]. Potential Effect on System NMIs may be inadvertently enabled or disabled contrary to the intended error handling intentions and capabilities of the platform.
46837 SB700 Family Product Errata 31 Rev. 1.0 March 2010 Indeterminate Boot Up State of RTC Bank Selection Bit (DV0) Description The RTC Bank Selection (DV0) bit (RTC_Reg:0A[4]) is not guaranteed to be initialized to the default value (DV0 = 0) by hardware on power cycles involving a VBAT power ramp (i.e., the first power up after the RTC battery is first installed or after the CMOS is cleared via a motherboard jumper).
