Specifications

© 2008 Advanced Micro Devices Inc.
Sample Programs
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 91
mov Byte PTR es:[ebp+ATI_PCIE_BAR3+ATI_SMBUS_BUS_DEV_FUN shl 12 \
+SB600_SMBUS_REGFC], 11111111b ; Set to GPIO
call ATI_fixed_delay_1ms_far ; Wait 1ms
mov ecx, dword PTR es:[ebp+ATI_PCIE_BAR3+ATI_SMBUS_BUS_DEV_FUN shl 12 \
+SB600_SMBUS_REGFC]
shr ecx,10h
mov di,cx ; Save GPIO lines status at di[7:0]
mov Byte PTR es:[ebp+ATI_PCIE_BAR3+ATI_SMBUS_BUS_DEV_FUN shl 12 \
+ATI_AZALIA_ExtBlk_DATA], 10101010b ; Set pin to HD Audio
; Interrupt routing table for HD Audio is at SMBUS ( Dev 14h, func 0) register 63h
mov Byte PTR es:[ebp+ATI_PCIE_BAR3+ATI_SMBUS_BUS_DEV_FUN shl 12 + 063h], 0
; Set PCI routing to #INTA
; Attempt to exit the reset state. This is done by command to exit the reset state and waiting
; for status of ready to begin operation.
mov ecx, 10 ; Make up to 10 attempt to exit reset state
re_do_reset:
and bx, BIT15+BIT14 ; Clear bit0-13
or Byte PTR ES:[ebx+08h], BIT0 ; Exit the reset state
call ATI_fixed_delay_1ms_far ; Wait 1ms
test Byte PTR ES:[ebx+08h], BIT0 ; Read of 1 = Ready to begin operation
jnz @f ; Go if reset bit is set
loop re_do_reset ; Wait until ready to begin operation
jmp ATI_SB_Cfg_Azalia_exit ; Exit because reset bit can not be set
; Ready to begin operation.
; Check codecs present by examining memory mapped register (pointed by EBX) at 0Eh
@@:
call ATI_fixed_delay_1ms_far ; Wait 1ms
mov al, Byte PTR ES:[ebx+0eh] ; State change status register
and al, 0fh ; Bits 3:0 are for state change status
jnz At_least_one_azalia ; Codec present
; Disable Azalia controller and leave
DisableAzaliaController:
; Clear memory access at PCI register 04
and Word PTR es:[ebp+ATI_PCIE_BAR3+ATI_AZALIA_BUS_DEV_FUN shl 12 +04h], 0
; Disable HD Audio module through PMIO register 59h bit 3
mov dx,0cd6h ; PMIO index register
mov al,59h ; Set PMIO index to 59h
out dx,al ;
mov dx,0cd7h ; PMIO data register
in al,dx ; Read current data