Specifications

© 2008 Advanced Micro Devices Inc.
Sample Programs
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 85
14.8.2 Initialize Southbridge Registers for SMI#
; Enable the base address range (228h-22Fh) in the LPC register.
; Address range 228h-22Fh is enabled in LPC Device 14h, function 3, Register 45h, bit 1
mov dx,0CF8h ; PCI device access index register
mov eax,8000A344h ; Device 14h, function 3, registers 44h-47h
out dx,eax
mov dx,0CFDh ; To access register 45h
in al,dx ; Read register 45h
or al,02h ; Set bit 1
out dx,al
; Configure ExtEvent1 for SMI#. ExtEvent1 is configured through PMIO
; register 32h bit 3:2 = 00
mov dx,0cd6h
mov al,32h
out dx,al
mov dx,0cd7h
in al,dx
and al,0f3h ; Clear bits 3:2
or al,04h ; Set [3:2] = 01 for SMI
out dx,al
; Set ExtEvent1 for SMI, negative edge through PMIO register 37h, bit 1 = 0
mov dx,0cd6h
mov al,37h
out dx,al
mov dx,0cd7h
in al,dx
and al,0fdh ; Clear bit 1 for Negative edge
out dx,al
; Also set PMIO register 04 to enable ExtEvent1 for SMI
mov dx,0cd6h
mov al,04h
out dx,al
mov dx,0cd7h
in al,dx
or al,02h
out dx,al
; End of temperature setting program.