Specifications

© 2008 Advanced Micro Devices Inc.
Sample Programs
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 64
Reg 43h Secondary master timing
Reg 4Ah, bits[2:0] Primary master mode number
Reg 4Ah bits[6:4] Primary slave mode number
Reg 4Bh bits[2:0] Secondary master mode number
Reg 4Bh bits[6:4] Secondary slave mode number
PIO timing has two components – the command width, and the recovery width. The widths are
stated in number of cycles of PCICLK and the following values are defined for PCICLK
frequency of 33MHz and 66MHz:
Width PIO Mode 4 PIO Mode 3 PIO Mode 2 PIO Mode 1 PIO Mode 0
Command
Width (cycles)
2 2 3 4 5
Recovery
Width
0 2 4 7 Dh
Sample program: Set primary master to PIO mode 4
; Set register 41h with timing and 4Ah, bits[2:0] with mode number
mov dx,0CF8h ; To set PCI configuration space index
mov eax,8000A140h ; To access registers 40h-43h
out dx,eax
mov dx,0CFDh ; To access PCI configuration space data at 41h
mov al,20h ; Timing for mode 4 (See table above)
out dx,al ; Set PIO timing
mov dx,0CF8h ; To set PCI configuration space index
mov eax,8000A148h ; To access registers 48-4Bh
out dx,eax ;
mov dx,0CFEh ; To access register 4Ah
in al,dx ; Read current value
and al,0F8h ; Clear bits 2:0
or al,4h ; Set to mode 4
out dx,al ;