Specifications

© 2008 Advanced Micro Devices Inc.
Sample Programs
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 63
14.2.9 Enable OHCI Controller
OHCI Device 13h, function 1 and 5, may be enabled/disabled by bits 1 and 5 in SMBus device
14h, function 0, register 068h.
If disable is done after BAR resources are allocated, set BAR to zero.
USB SMI enabled, when appropriate, at SMBus device 14h, function 0, register 65h, bit 7.
Sample Program:
Enable 5 OHCIs .
EnableOhciSample proc near
push eax ; Save registers used in this program
push dx
mov dx,0CF8h ; To access PCI configuration space
mov eax,8000A068h ; SMBus device 14h, function 0, register 68h
out dx,eax
mov dx,0CFCh ; To read register 068h
in al,dx ;
or al,03Eh ; Set bit [5:1] to enable OHCI
out dx,al
pop dx
pop eax
ret
EnableOhciSample endp
14.3 IDE Settings
The primary IDE channel is enabled on power-up by default. Refer to section 14.3.4 to disable
the IDE channels.
14.3.1 PIO Mode Settings
IDE PIO mode and timing is set through the registers 40h-43h, 4Ah-4Bh, the PIO timing is
programmed in registers 40h-43h, and PIO mode is programmed in registers 4Ah–4Bh.
The PCI IDE device is 14h, function 1.
Reg 40h Primary slave timing
Reg 41h Primary master timing
Reg 42h Secondary slave timing