Specifications

© 2008 Advanced Micro Devices Inc.
Sample Programs
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 57
14.2.3 C3 Support
The C3 support depends on the processor PBE support and HyperThreading. The ACPI FACP
table also needs to be modified for C3 support. The description below applies only to the SB600
registers affected by C3 support.
PM I/O register 51h is set to C3 latency as follows:
C3 Latency = (bits[5:0] of PM I/O register 51h) * 8us
Hence for recommended C3 Latency = 40us, set (bits[5:0] of PM I/O register 51h) = 5
For deep C3 support, in addition to setting register 51h above, PM I/O register 50h bit0 must also
be set to 1.
14.2.4 Subtractive Decoding for P2P Bridge
To enable the subtractive decoding, set device 14h, function 4, P2P bridge register 40h bit 5 to 1.
Sample Program:
EnableSubtractiveDecoding proc near
push eax ; Save registers used in this routine
push dx
mov dx,0CF8h
mov eax,8000A440h ; Bus 0, device 14h, function 4, register 40h, P2P
out dx,eax
mov dx,0CFCh ; To access register 40h
in al,dx
or al,20h ; Set bit 5 for subtractive decoding
out dx,al
; Set bit 7 of register 4Bh to show subtractive decoding in class code reg. 09h bit 0
mov dx,0CF8h
mov eax,8000A448h ; Bus 0, device 14h, function 4, register 48h-4Bh
out dx,eax
mov dx,0CFFh ; To access register 4Bh
in al,dx
or al,80h ; Control bit for PI register
out dx,al