Specifications

© 2008 Advanced Micro Devices Inc.
Common Interface Module – CIM-SB600
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 51
13.4 CIM-SB600 SBPOR Sub-Module
Southbridge Power-On Reset initialization (SBPOR) is designed to support initialization of Southbridge
registers common across all platforms. Design take in to consideration that code will be executed in
stackless environment. There is no inputs requirement for this module except that the return address
should be setup in SP.
Module files: SB_POR.INC
Support files: SB_CMN.INC, ATISBCFG.INC
13.4.1 SBPOR Interface
ATISBPowerOnResetInitJSP – This routine initializes all the Southbridge device registers (including
ACPI Base Address registers, PMIO registers) and applies LPC-DMA deadlock workaround. This
routine should be called before the BIOS decides whether it is normal POST or S3 resume.
13.5 CIM-SB600 SB POST Initialize Sub-Module
SB POST Initialization module consists of three parts:
1. Early POST (Before PCI enumeration in system BIOS).
2. Mid POST (After PCI enumeration in system BIOS).
3. Late POST(Before BIOS gives control to bootloader)
All the PCI configuration access is done using the memory mapped PCI configuration space.
Module files: ATISBPT.INC, AM97POST.INC, AZALIAP.INC, SATAPOST.INC, USBPOST.INC
Support files: SB_CFG.INC, ATISBCFG.INC, SB_CMN.INC, SB_CMNPT.INC
The entire POST initialization module is needed only during POST and it can be discarded at end of
POST.
13.5.1 Requirements
The following requirements should be met before calling any interface in the SB POST initialization
module.
1. Module required stack to be present to operate.
2. Input Data Structure (ATI_SB_CFG_SETUP_SETTING) should be initialized before doing any
interface to this module.
3. System should be in 4GB flat mode (also called as Big Real Mode).
4. PCIE BAR should be initialized before calling any interface in this module.