Specifications

© 2008 Advanced Micro Devices Inc.
Table of Contents
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 4
6.1 IDE Channel Enable/Disable.......................................................................................................27
6.1.1 IDE Channel Enable ............................................................................................................................27
6.1.2 IDE Channel Disable...........................................................................................................................27
6.2 PIO Modes...................................................................................................................................28
6.2.1 PIO Mode ............................................................................................................................................28
6.2.2 PIO Timing..........................................................................................................................................28
6.3 DMA Modes................................................................................................................................28
6.3.1 Legacy (Multi-Words) DMA mode.....................................................................................................28
6.3.2 Ultra-DMA Mode................................................................................................................................29
7 Serial ATA (SATA) ...................................................................................................30
7.1 SATA Hot Plug...........................................................................................................................30
7.1.1 Sample Code........................................................................................................................................30
8 Power Management...................................................................................................31
8.1 SMI Handling – EOS (PM IO Reg10h[Bit0]).............................................................................31
8.2 Programmable I/Os......................................................................................................................31
8.3 Power Management Timers.........................................................................................................32
8.3.1 PM Timer 1 (Inactivity Timer) ............................................................................................................32
8.3.2 PM Timer 2 (Activity Timer) ..............................................................................................................32
8.4 SMI Events..................................................................................................................................32
8.4.1 Power Button .......................................................................................................................................34
8.5 C-State Break Events ..................................................................................................................34
8.5.1 Break Events for C2 State....................................................................................................................34
8.5.2 Break Events for C3 and C4 States......................................................................................................34
8.6 Save/Restore Sequence for S3 State............................................................................................34
8.6.1 Register Save Sequence for S3 State...................................................................................................34
8.7 Wake on Events...........................................................................................................................35
8.8 Sleep SMI Events........................................................................................................................35
8.8.1 Sleep SMI Control Register.................................................................................................................35
8.8.2 Sleep SMI Programming Sequence .....................................................................................................35
8.8.2.1 Set Sleep SMI Control Register...................................................................................................35
8.8.2.2 Enter Sleep SMI# Routine...........................................................................................................35
9 APIC Programming..................................................................................................37
9.1 Northbridge APIC Enable ...........................................................................................................37
9.2 Southbridge APIC Enable...........................................................................................................37
9.3 IOAPIC Base Address.................................................................................................................37
9.4 APIC IRQ Assignment................................................................................................................37
9.5 APIC IRQ Routing......................................................................................................................38
10 Watchdog Timer........................................................................................................39
11 A-Link Bridge............................................................................................................41
11.1 A-Link Registers .........................................................................................................................41
11.2 Programming Procedure..............................................................................................................42