Specifications

© 2008 Advanced Micro Devices Inc.
Power Management
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 35
• PCI registers not on the SB600
• Super I/O and other I/O registers.
The BIOS typically sets aside an area in the memory to save the registers prior to the S3 state.
The Southbridge registers may be saved in any order as long as those registers are visible to the
BIOS.
Some of the registers, such as SubSystem ID and SubSystem Vendor ID, may be saved, but
written only once as dword. They are handled separately during restore.
8.7 Wake on Events
TBD
8.8 Sleep SMI Events
These events provide an SMI# before the system transits to an SX state (e.g. ACPI S1, S2,
S3, S4, and S5). This feature helps the System BIOS to develop software workarounds or
debugging routines before the system goes to sleep state.
8.8.1 Sleep SMI Control Register
There is a Sleep SMI control register in the SB600. Its base I/O address is defined at PMIO Reg
0x04.
SLP_SMI_EN is a R/W register bit for controlling a Sleep SMI when the system transits to an
ACPI SX state. The register definition is as follows:
• SLP_SMI_EN [Bit7] = 0, Disables Sleep SMI event.
• SLP_SMI_EN [Bit7] = 1, Enables Sleep SMI event.
There is a Sleep SMI Status register in the SB600. Its base I/O address is defined at PMIO Reg
0x07.
SLP_SMI_Status [Bit7] is asserted when the system goes to an ACPI SX state, and when
SLP_SMI_EN is set to enable.
8.8.2 Sleep SMI Programming Sequence
8.8.2.1 Set Sleep SMI Control Register
The Sleep SMI Control Register does not necessary have to be enabled before the system goes to
the ACPI SX state. One may enable the control the bit in the ACPI ASL code. Please refer to
section 14.9 “Sleep Trap Through SMI#” for the sample code.
8.8.2.2 Enter Sleep SMI# Routine
The system does not go into the sleep state (set by ACPI PM1_CNT) when SMI# is asserted. The