Specifications

© 2008 Advanced Micro Devices Inc.
PCI IRQ Routing
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 21
4 PCI IRQ Routing
4.1 PCI IRQ Routing Registers
The SB600 uses one pair of I/O ports to do the PCI IRQ routing. The ports are at C00h/C01h.
Address Register Name Description
C00h PCI_Intr_Index PCI IRQ Routing Index
0 – INTA#
1 – INTB#
2 – INTC#
3 – INTD#
4 – SCI
5 – SMBus interrupt
9 – INTE#
0Ah – INTF#
0Bh – INTG#
0Ch – INTH#
C01h PCI_Intr_Data 0 ~ 15 : IRQ0 to IRQ15
IRQ0, 2, 8, 13 are reserved
4.2 PCI IRQ BIOS Programming
PCI IRQs are assigned to interrupt lines using I/O ports at C00h and C01h in index/data format.
The register C00h is used for index as written with index number 0 through 0Ch as described in
section 4.1 above. Register C01h is written with the interrupt number as data.
The following assembly language example assigns INTB# line to interrupt 10 (0Ah).
mov dx,0C00h ; To write to IO port C00h
mov al,02h ; Index for PCI IRQ INTB# as defined in section 4.1
out dx,al ; Index is now set for INTB#
mov dx,0C01h ; To write interrupt number 10 (0Ah)
mov al,0Ah ; Data is interrupt number 10 (0Ah )
out dx,al ; Assign IRQB# to interrupt 10