Specifications

© 2008 Advanced Micro Devices Inc.
SB600 Early-POST Initialization
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 18
3.3 BIOS RAM
The SB600 has 256 bytes of BIOS RAM. Data in this RAM is preserved until RSMRST# or S5 is
asserted, or until power is lost.
This RAM is accessed using index and data registers at CD4h/CD5h.
3.4 Serial IRQ
The SB600 supports serial IRQ, which allows one single signal to report multiple interrupt
requests. The SB600 supports a message for 21 serial interrupts, which include 15 IRQs, SMI#,
IOCHK#, and 4 PCI interrupts.
SMBus PCI Reg69h is used for setting serial IRQ.
Bits in SMBus
PCI Reg69
Description
Power-on
Default
Recommended
Value
7 1 – Enables the serial IRQ function
0 – Disables the serial IRQ function
0 1
6 1 – Active (quiet) mode
0 – Continuous mode
0 0
5:2 Total number of serial IRQs = 17 +
NumSerIrqBits
0 – 17 serial IRQs (15 IRQs, SMI#,
IOCHK#)
1 – 18 serial IRQs (15 IRQs, SMI#,
IOCHK#, INTA#)
...
15 - 32 serial IRQ's
The SB600 serial IRQ can support 15
IRQs, SMI#, IOCHK#, INTA#,
INTB#, INTC#, and INTD#.
0 0100b
1:0 Number of clocks in the start frame 0 00b
Note: The BIOS should enter the continuous mode first when enabling the serial IRQ protocol, so that the
SB600 can generate the start frame.