Specifications

© 2008 Advanced Micro Devices Inc.
SB600 Early-POST Initialization
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 17
3.2 Real Time Clock (RTC)
3.2.1 RTC Access
The internal RTC is divided into two sections: the clock and alarm function (registers 0 to 0Dh),
and CMOS memory (registers 0Eh to FFh). The clock and alarm functions must be accessed
through I/O ports 70h/71h. The CMOS memory (registers 0Eh to FFh) should be accessed
through I/O ports 72h/73h.
3.2.1.1 Special Locked Area in CMOS
Some CMOS memory locations may be disabled for read/write. Register 6Ah of SMBus (Bus 0,
Device 14h, Function 0) has bits to disable these CMOS memory locations. These bits can be
written only once after each power up reset or PCI reset.
RTCProtect- RW - 8 bits - [PCI_Reg: 6Ah]
Field Name Bits Default Description
RTCProtect 0 0h When set, RTC RAM index 38h:3Fh will be locked from
read/write. This bit can only be written once.
RTCProtect 1 0h When set, RTC RAM index F0h:FFh will be locked from
read/write. This bit can only be written once.
RTCProtect 2 0h When set, RTC RAM index E0h:EFh will be locked from
read/write. This bit can only be written once.
RTCProtect 3 0h When set, RTC RAM index D0h:DFh will be locked from
read/write. This bit can only be written once.
RTCProtect 4 0h When set, RTC RAM index C0h:CFh will be locked from
read/write. This bit can only be written once.
Reserved 7:5 0h
3.2.1.2 Century Byte
The RTC has a century byte at CMOS location 32h. Century is stored in a single byte and the
BCD format is used for the century (for example, 20h for the year 20xx). This byte is accessed
using I/O ports 70h and 71h. (The BIOS must set PMIO register 7Ch bit 4 to 1 to use this century
byte at CMOS location 32h
3.2.1.3 Date Alarm
The RTC has a date alarm byte. This byte is accessed as follows:
1. Set to 1 the RTC register 0Ah , bit 4, using I/O ports 70h and 71h.
2. Write Date Alarm in BCD to register 0Dh using I/O ports 70h and 71h.
3. Clear to 0 the RTC register 0Ah bit 4 using I/O ports 70h and 71h.
Note: It is important to clear RTC register 0Ah bit 4 to zero; otherwise, the CMOS memory may
not be accessed correctly from this point onward.