Specifications

© 2008 Advanced Micro Devices Inc.
SB600 Programming Architecture
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 14
* Note:
• The SMI CMD Block must be defined on the 16-bit boundary, i.e., the least significant nibble
of the address must be zero (for example, B0h, C0h etc.)
• The SMI CMD Block consists of two ports – the SMI Command Port at base address, and the
SMI Status Port at base address+1.
• The writes to SMI Status Port will not generate an SMI. The writes to the SMI Command
Port will generate an SMI.
• The SMI Command and SMI Status ports may be written individually as 8 bit ports, or
together as a 16-bit port.
2.3 Memory Map
Memory Range Description Enable Bit
0000 0000h-000D FFFFh
0010 0000h- TOM
Main System Memory
000E 0000h-000F FFFFh Either PCI ROM or LPC
ROM
PCI ROM : SMBus PCI Reg41h[Bit4]
LPC ROM : LPC Reg68h & LPC_Rom strap
FFC0 0000h-FFC7 FFFFh
FF80 0000h-FF87 FFFFh
FWH LPC Reg70h[3:0]
FFC8 0000h-FFCF FFFFh
FF88 0000h-FF8F FFFFh
FWH LPC Reg70h[7:4]
FFD0 0000h-FFD7 FFFFh
FF90 0000h-FF97 FFFFh
FWH LPC Reg70h[11:8]
FFD8 0000h-FFDF FFFFh
FF98 0000h-FF9F FFFFh
FWH LPC Reg70h[15:12]
FFE0 0000h-FFE7 FFFFh
FFA0 0000h-FFA7 FFFFh
FWH LPC Reg70h[19:16]
FFE8 0000h-FFEF FFFFh
FFA8 0000h-FFAF FFFFh
FWH LPC Reg70H[23:20]
FFF0 0000h-FFF7 FFFFh
FFB0 0000h-FFB7 FFFFh
FWH LPC Reg70h[27:24]
FFF8 0000h-FFFF FFFFh
FFB8 0000h-FFBF FFFFh
FWH LPC Reg70h[31:28]