User`s manual

VIA KT133 ATX MAINBOARD AWARD BIOS
4-12
This item allows you to control the onboard AC 97 audio.
OnChip Modem
This item allows you to control the onboard MC 97 Modem.
CPU to PCI Write buffer
When this field is Enabled, writes from the CPU to the PCI bus are buffered, to
compensate for the speed differences between the CPU and the PCI bus. When
Disabled, the writes are not buffered and the CPU must wait until the write is
complete before starting another write cycle.
PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer. Burstable
transactions then burst on the PCI bus and non-burstable transactions don’t.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait states.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification
version 2.1.
PCI#2 Access #1 Retry
When disabled, PCI#2 will not be disconnected until access finishes (difault).
When enabled, PCI#2 will be disconnected if max retries are attempted without
success.
AGP Master 1 WS Write
When Enabled, writes to the AGP(Accelerated Graphics Port) are executed with
one wait states.
AGP Master 1 WS Read
When Enabled, read to the AGP (Accelerated Graphics Port) are executed with
one wait states.