User`s manual

VIA KT133 ATX MAINBOARD AWARD BIOS
4-10
DRAM Timing By SPD
When enabled, the system BIOS will read the DRAM parameters from the SPD
chip on the DIMM module and set the DRAM timing automatically.
DRAM Clock
This field allows you to select the DRAM access speed to control the memory
performance.
DRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the default
value specified unless you have the technical background.
BANK Interleave
This field allows you to select how many bank of DRAM is installed on the
mainboard so that the system BIOS will be able to adjust the SDRAM interleave
access mode to optimize the SDRAM performance.
Memory Hole
In order to improve performance, certain space in memory is reserved for ISA
cards. This memory must be mapped into the memory space below 16MB. This
field allows you to enable of disable the memory mapping.
Enabled: The memory space between 15 ~ 16MB will be remapped for ISA cards.
Disabled: No memory will be remapped.
PCI Master Pipeline Req
This field allows you to enable or disable the PCI pipeline access.
P2C/C2P Concurrency
This selection field allows you to enable/disable the PCI to CPU, CPU to PCI
concurrency.
Fast R-W Turn Around
This item controls the DRAM timing. It allows you to enable/ disable the fast
read/write turn around.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.