Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
99
A.4 AERR# (I/O)
The AERR# signal is the address parity error signal.
Assuming the AERR# driver is enabled during the
power-on configuration, a bus agent can drive
AERR# active for exactly one clock during the Error
Phase of a transaction. AERR# must be inactive for
a minimum of two clocks. The Error Phase is always
three clocks from the beginning of the Request
Phase.
On observing active ADS#, all agents begin parity
and protocol checks for the signals valid in the two
Request Phase clocks. Parity is checked on
AP[1:0]# and RP# signals. AP1# protects A[35:24]#,
AP0# protects A[23:3]# and RP# protects REQ[4:0]#.
A parity error without a protocol violation is signaled
by AERR# assertion.
If AERR# observation is enabled during power-on
configuration, AERR# assertion in a valid Error
Phase aborts the transaction. All bus agents remove
the transaction from the In-order Queue and update
internal counters. The Snoop Phase, Response
Phase, and Data Phase of the transaction are
aborted. All signals in these phases must be
deasserted two clocks after AERR# is asserted,
even if the signals have been asserted before
AERR# has been observed. Specifically if the Snoop
Phase associated with the aborted transaction is
driven in the next clock, the snoop results, including
a STALL condition (HIT# and HITM# asserted for
one clock), are ignored. All bus agents must also
begin an arbitration reset sequence and deassert
BREQn#/BPRI# arbitration signals on sampling
AERR# active. A current bus owner in the middle of a
bus lock operation must keep LOCK# asserted and
assert its arbitration request BPRI#/BREQn# after
keeping it inactive for two clocks to retain its bus
ownership and guarantee lock atomicity. All other
agents, including the current bus owner not in the
middle of a bus lock operation, must wait at least 4
clocks before asserting BPRI#/BREQn# and
beginning a new arbitration.
If AERR# observation is enabled, the request initiator
can retry the transaction up to n times until it reaches
the retry limit defined by its implementation. (The
Pentium Pro processor retries once.) After n retries,
the request initiator treats the error as a hard error.
The request initiator asserts BERR# or enters the
Machine Check Exception handler, as defined by the
system configuration.
If AERR# observation is disabled during power-on
configuration, AERR# assertion is ignored by all bus
agents except a central agent. Based on the Machine
Check Architecture of the system, the central agent
can ignore AERR#, assert NMI to execute NMI
handler, or assert BINIT# to reset the bus units of all
agents and execute an MCE handler.
A.5 AP[1:0]# (I/O)
The AP[1:0]# signals are the address parity signals.
They are driven by the request initiator during the two
Request Phase clocks along with ADS#, A[35:3]#,
REQ[4:0]#, and RP#. AP1# covers A[35:24]#. AP0#
covers A[23:3]#. A correct parity signal is high if an
even number of covered signals are low and low if an
odd number of covered signals are low. This rule
allows parity to be high when all the covered signals
are high.
Provided “AERR# drive” is enabled during the power-
on configuration, all bus agents begin parity checking
on observing active ADS# and determine if there is a
parity error. On observing a parity error on any one of
the two Request Phase clocks, the bus agent asserts
AERR# during the Error Phase of the transaction.
A.6 ASZ[1:0]# (I/O)
The ASZ[1:0]# signals are the memory address-
space size signals. They are driven by the request
initiator during the first Request Phase clock on the
REQa[4:3]# pins. The ASZ[1:0]# signals are valid
only when REQa[1:0]# signals equal 01B, 10B, or
11B, indicating a memory access transaction. The
ASZ[1:0]# decode is defined in Table 45.
Table 45. ASZ[1:0]# Signal Decode
ASZ[1:0]# Description
0
0
0 <= A[35:3]# < 4 GB
0
1
4 GB <= A[35:3]# < 64 GB
1
X
Reserved
If the memory access is within the 0-to-(4GByte -1)
address space, ASZ[1:0]# must be 00B. If the
memory access is within the 4Gbyte-to-(64GByte -1)
address space, ASZ[1:0]# must be 01B. All
observing bus agents that support the 4Gbyte (32 bit)
address space must respond to the transaction only