Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
98
Snoop requests and cache-line writeback
transactions are unaffected by A20M# input. Address
20 is not masked when the processor samples
external addresses to perform internal snooping.
A20M# is an asynchronous input. However, to
guarantee recognition of this signal following an I/O
write instruction, A20M# must be valid with active
RS[2:0]# signals of the corresponding I/O Write bus
transaction. In FRC mode, A20M# must be
synchronous to BCLK.
During active RESET#, the Pentium Pro processor
begins sampling the A20M#, IGNNE#, and LINT[1:0]
values to determine the ratio of core-clock frequency
to bus-clock frequency. After the PLL-lock time, the
core clock becomes stable and is locked to the
external bus clock. On the active-to-inactive
transition of RESET#, the Pentium Pro processor
latches A20M#, IGNNE#, and LINT[1:0] and freezes
the frequency ratio internally. 29See Table 44.
A.3 ADS# (I/O)
The ADS# signal is the address Strobe signal. It is
asserted by the current bus owner for one clock to
indicate a new Request Phase. A new Request
Phase can only begin if the In-order Queue has less
than the maximum number of entries defined by the
power-on configuration (1 or 8), the Request Phase
is not being stalled by an active BNR# sequence and
the ADS# associated with the previous Request
Phase is sampled inactive. Along with the ADS#, the
request initiator drives A[35:3]#, REQ[4:0]#,
AP[1:0]#, and RP# signals for two clocks. During the
second Request Phase clock, ADS# must be
inactive. RP# provides parity protection for
REQ[4:0]# and ADS# signals during both clocks. If
the transaction is part of a bus locked operation,
LOCK# must be active with ADS#.
If the request initiator continues to own the bus after
the first Request Phase, it can issue a new request
every three clocks. If the request initiator needs to
release the bus ownership after the Request Phase,
it can deactivate its BREQn#/ BPRI# arbitration
signal as early as with the activation of ADS#.
All bus agents observe the ADS# activation to begin
parity checking, protocol checking, address decode,
internal snoop, or deferred reply ID match operations
associated with the new transaction. On sampling the
asserted ADS#, all agents load the new transaction
in the In-order Queue and update internal counters.
The Error, Snoop, Response, and Data Phase of the
transaction are defined with respect to ADS#
assertion.
Table 44. Bus Clock Ratios Versus Pin Logic Levels
Ratio of Core Clock
to Bus Clock
LINT[1]/NMI LINT[0]/INTR
IGNNE#
A20M#
2LL
L
L
2HH
H
H
3LL
H
L
4LL
L
H
RESERVED L L
H
H
5/2 L H
L
L
7/2 L H
H
L
RESERVED L H
L
H
RESERVED L H
H
H
RESERVED ALL OTHER COMBINATIONS