Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
97
APPENDIX A
This appendix provides an alphabetical listing of all
Pentium Pro processor signals. Pins that do not
appear here are not considered bus signals and
are described in Table 2.
A.1 A[35:3]# (I/O)
The A[35:3]# signals are the address signals. They
are driven during the two-clock Request Phase by
the request initiator. The signals in the two clocks are
referenced Aa[35:3]# and Ab[35:3]#. During both
clocks, A[35:24]# signals are protected with the
AP1# parity signal, and A[23:3]# signals are
protected with the AP0# parity signal.
The Aa[35:3]# signals are interpreted based on
information carried during the first Request Phase
clock on the REQa[4:0]# signals.
For memory transactions as defined by REQa[4:0]#
= {XX01X,XX10X,XX11X}, the Aa[35:3]# signals
define a 2
36
-byte physical memory address space.
The cacheable agents in the system observe the
Aa[35:3]# signals and begin an internal snoop. The
memory agents in the system observe the Aa[35:3]#
signals and begin address decode to determine if
they are responsible for the transaction completion.
Aa[4:3]# signals define the critical word, the first data
chunk to be transferred on the data bus. Cache line
transactions use the standard burst order described
in
Pentium® Pro Processor Developer’s Manual,
Volume 1: Specifications (Order
Number 242690) to
transfer the remaining three data chunks.
For Pentium Pro processor IO transactions as
defined by REQa[4:0]# = 1000X, the signals
Aa[16:3]# define a 64K+3 byte physical IO space.
The IO agents in the system observe the signals and
begin address decode to determine if they are
responsible for the transaction completion.
Aa[35:17]# are always zero. Aa16# is zero unless
the IO space being accessed is the first three bytes
of a 64KByte address range.
For deferred reply transactions as defined by
REQa[4:0]# = 00000, Aa[23:16]# carry the deferred
ID. This signal is the same deferred ID supplied by
the request initiator of the original transaction on
Ab[23:16]#/DID[7:0]# signals. Pentium Pro processor
bus agents that support deferred replies sample the
deferred ID and perform an internal match against
any outstanding transactions waiting for deferred
replies. During a deferred reply, Aa[35:24]# and
Aa[15:3]# are reserved.
For the branch-trace message transaction as defined
by REQa[4:0]# = 01001 and for special and interrupt
acknowledge transactions, as defined by REQa[4:0]#
= 01000, the Aa[35:3]# signals are reserved and
undefined.
During the second clock of the Request Phase,
Ab[35:3]# signals perform identical signal functions
for all transactions. For ease of description, these
functions are described using new signal names.
Ab[31:24]# are renamed the attribute signals
ATTR[7:0]#. Ab[23:16]# are renamed the Deferred ID
signals DID[7:0]#. Ab[15:8]# are renamed the eight-
byte enable signals BE[7:0]#. Ab[7:3]# are renamed
the extended function signals EXF[4:0]#.
Table 43. Request Phase Decode
Ab[31:24]# Ab[23:16]#
Ab[15:8]#
Ab[7:3]#
ATTR[7:0]# DID[7:0]#
BE[7:0]#
EXF[4:0]#
On the active-to-inactive transition of RESET#, each
Pentium Pro processor bus agent samples A[35:3]#
signals to determine its power-on configuration.
A.2 A20M# (I)
The A20M# signal is the address-20 mask signal in
the PC Compatibility group. If the A20M# input signal
is asserted, the Pentium Pro processor masks
physical address bit 20 (A20#) before looking up a
line in any internal cache and before driving a
read/write transaction on the bus. Asserting A20M#
emulates the 8086 processor’s address wrap around
at the one Mbyte boundary. Only assert A20M# when
the processor is in real mode. The effect of asserting
A20M# in protected mode is undefined and may be
implemented differently in future processors.