Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
7
Bus Interface Unit
Fetch Load Store
L1 ICache L1 DCache
L2 Cache
System Bus
Dispatch
/Execute
Unit
Retire
Unit
Instruction
Pool
Fetch/
Decode
Unit
Figure 2. The Three Core Engines Interface with Memory via Unified Caches
••
2.2.1. THE FETCH/DECODE UNIT
Figure 3 shows a more detailed view of the
Fetch/Decode Unit.
The ICache is a local instruction cache. The Next_IP
unit provides the ICache index, based on inputs from
the Branch Target Buffer (BTB), trap/interrupt status,
and branch-misprediction indications from the integer
execution section.