Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz

T5 load2a 0 p6_2 0 Z0=200 TD=8.5ps $ Bondwire

CCPU_2 p6_2 0 4pf $ CPU input capacitance

T6 line2 0 line3 0 Z0=72 TD=568ps $ PCB trace between packages

T7 line3 0 load3 0 Z0=50 TD=50ps $ PCB trace from via to landing pad

T8 load3 0 asic_1 0 Z0=75 TD=180PS $ ASIC package

CASIC_1 asic_1 0 6.5PF $ ASIC input capacitance (die capacitance)

T9 line3 0 line4 0 Z0=72 TD=403PS $ PCB trace between packages

T10 line4 0 load4 0 Z0=50 TD=50PS $ PCB trace from via to landing pad

T11 load4 0 asic_2 0 Z0=75 TD=180PS $ ASIC package

CASIC_2 asic_2 0 6.5PF $ ASIC input capacitance (die capacitance)

T12 line4 0 line5 0 Z0=72 TD=403PS $ PCB trace between packages

T13 line5 0 load5 0 Z0=50 TD=50PS $ PCB trace from via to landing pad

T14 load5 0 asic_3 0 Z0=75 TD=180PS $

Replace these two lines with

CASIC_3 asic_3 0 6.5PF $

the equivalent model for your package.

(This model should include the package

pin, package trace, bond wire and any die

capacitance that is not already included

in your driver model.)

T15 line5 0 line6 0 Z0=72 TD=403PS $ PCB trace between packages

T16 line6 0 load6 0 Z0=50 TD=50PS $ PCB trace from via to landing pad

T17 load6 0 asic_4 0 Z0=75 TD=180PS $ ASIC package

CASIC_4 asic_4 0 6.5PF $ ASIC input capacitance

T18 line6 0 line7 0 Z0=72 TD=403PS $ PCB trace between packages

X3 line7 load7 socket $ Socket model

T19 load7 0 load7a 0 Z0=42 TD=230PS $ CPU worst case package

T20 load7a 0 p6_3 0 Z0=200 TD=8.5PS $ Bondwire

CCPU_3 p6_3 0 4PF $ CPU input capacitance

T21 line7 0 line8 0 Z0=72 TD=568PS $ PCB trace between packages

X4 line8 load8 socket $ Socket model

T22 load8 0 load8a 0 Z0=42 TD=230PS $ CPU worst case package

T23 load8a 0 p6_4 0 Z0=200 TD=8.5PS $ Bondwire

CCPU_4 p6_4 0 4PF $ CPU input capacitance

T24 line8 0 R_TERM 0 Z0=72 TD=75PS $ PCB trace to termination resistor

Rterm1 R_TERM vpu (R=42) $ Pull-up termination resistance

CRTERM1 R_TERM vpu (C=2PF) $ Pull-up termination capacitance

Rout bond asic_3.001

.subckt socket in out $ Socket model