Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
53
V
REF
V
REF
+ 0.2
V
REF
− 0.2
Time
1.5 V Clk Ref
0
.3
V
/
ns
V
start
3
.0 V
/
ns
Clock
T
su
Figure 35. Standard Input Hi-to-Lo Waveform for Characterizing Receiver Setup Time
Hold time for GTL+ , T
HOLD
, is defined as:
The minimum time from the clock pin of the
receivers crossing of the 1.5 V level to the
receiver input signal pin crossing of V
REF
,
which guarantees that the input buffer has
captured new data at the receiver input
signal pin, given an infinite setup time.
Strictly speaking, hold time must be determined when
the input barely meets minimum setup time (see
definition of setup time above). However, for current
GTL+ systems, setup time is expected to be met,
well beyond the minimum required in cases where
hold is critical. This is because hold is critical when
the receiver is very close to the driver. In such
cases, the signal will arrive at the receiver shortly
after the clock, hence meeting setup time with
comfortable margin.
The recommended procedure for extracting T
HOLD
is
outlined below. If one employs additional steps, it
would be beneficial that any such extra steps be
documented with the results of this receiver
characterization:
1. The full receiver circuit must be used,
comprising the input differential amplifier, any
shaping logic gates, and the edge-triggered (or
pulse-triggered) flip-flop. The output of the flip-
flop must be monitored.
2. The receiver’s Lo-to-Hi hold time should be
determined using a nominal input waveform that
starts at V
IN_LOW_MAX
(V
REF
- 200 mV) and
goes to V
TT
, at a fast edge rate of 0.8V/ns, with
the process, temperature, voltage, and
V
REF_INTERNAL
of the receiver set to the fastest
(or best) corner values (yielding the longest
T
HOLD
). Here, V
REF
is the external (system)
reference voltage at the device pin. Due to
tolerance in V
TT
(1.5 V, ±10%) and the voltage
divider generating system V
REF
from V
TT
(±2%),
V
REF
can shift around 1 V by a maximum of
±122 mV. When determining hold time, the
internal reference voltage V
REF_INTERNAL
(at the
reference gate of the diff. amp.) must be set to
the value which yields the worst case hold time.
Here, V
REF_INTERNAL
= V
REF
± (122 mV
+V
NOISE
). Where, V
NOISE
is the net maximum
differential noise amplitude on the component’s
internal V
REF
distribution bus (at the amplifier’s
reference input gate) comprising noise picked
up by the connection from the V
REF
package pin
to the input of the amp.
3. Analogously, for the hold time of Hi-to-Lo
transitions, the input starts at V
IN_HIGH_MIN
=
V
REF
+200 mV and drops to < 0.5 V at the rate
of 3V/ns.