Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
51
Figure 33. Clock to Output Data Timing (T
CO
)
T
CO
measurement for a Lo-to-Hi signal transition is
shown in Figure 35. The T
CO
measurement for Hi-to-
Lo transitions is similar.
4.2.3.2. Minimum Setup and Hold Times
Setup time for GTL+ (T
SU
) is defined as:
The minimum time from the input signal pin
crossing of V
REF
to the clock pin of the
receiver crossing the 1.5 V level, which
guarantees that the input buffer has captured
new data at the input pin, given an infinite
hold time.
Strictly speaking, setup time must be determined
when the input barely meets minimum hold time (see
definition of hold time below). However, for current
GTL+ systems, hold time should be met well beyond
the minimum required in cases where setup is
critical. This is because setup is critical when the
receiver is far removed from the driver. In such
cases, the signal will be held at the receiver for a
long time after the clock, since the change needs a
long time to propagate from the driver to the receiver.
The recommended procedure for the I/O buffer
designer to extract T
SU
is outlined below. If one
employs additional steps, it would be beneficial that
any such extra steps be documented with the results
of this receiver characterization:
1. The full receiver circuit must be used,
comprising the input differential amplifier, any
shaping logic gates, and the edge-triggered (or
pulse-triggered) flip-flop. The output of the flip-
flop must be monitored.
2. The receiver’s Lo-to-Hi setup time should be
determined using a nominal input waveform like
the one shown in Figure 34 (solid line). The Lo-
to-Hi input starts at V
IN_LOW_MAX
(V
REF
-
200 mV) and goes to V
IN_HIGH_MIN
= V
REF
+200 mV, at a slow edge rate of 0.3 V/ns, with
the process, temperature, voltage, and
V
REF_INTERNAL
of the receiver set to the worst
(longest T
SU
) corner values. Here, V
REF
is the
external (system) reference voltage at the
device pin. Due to tolerance in V
TT
(1.5V,
±10%) and the voltage divider generating
system V
REF
from V
TT
(±2%), V
REF
can shift
around 1 V by a maximum of ±122 mV. When
determining setup time, the internal reference
voltage V
REF_INTERNAL
(at the reference gate of
the diff. amp.) must be set to the value which
yields the longest setup time. Here,
V
REF_INTERNAL
= V
REF
±(122 mV +V
NOISE
).
Where, V
NOISE
is the net maximum differential
noise amplitude on the component’s internal
V
REF
distribution bus (at the amplifier’s
reference input gate) comprising noise picked
up by the connection from the V
REF
package pin
to the input of the amp.
3. Analogously, for the setup time of Hi-to-Lo
transitions (Figure 35), the input starts at
V
IN_HIGH_MIN
= V
REF
+200 mV and drops to