Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
47
4.2.2. I/O Buffer AC Specification
Table 22 contains the I/O Buffer DC parameters.
Table 22. I/O Buffer AC Parameters
Symbol Parameter Min Max Unit
Figure
Notes
dV/dt
EDGE
Output Signal Edge Rate, rise 0.3 0.8 V/ns 1, 2, 3
dV/dt
EDGE
Output Signal Edge Rate, fall 0.3 –0.8 V/ns 1, 2, 3
T
CO
Output Clock to Data Time no spec ns
Figure 33
4, 5
T
SU
Input Setup Time no spec ns
Figure 24
Figure 25
4, 6
T
HOLD
Input Hold Time no spec ns 4, 6
NOTES:
1. This is the maximum instantaneous dV/dt over the entire transition range (Hi-to-Lo or Lo-to-Hi) as measured at the
driver’s output
pin while driving the Ref8N network, with the driver and its package model located near the center of the
network (see Section 4.4).
2. These are design targets. The acceptance of the buffer is also based on the resultant signal quality. In addition to edge
rate, the shape of the rising edge can also have a significant effect on the buffer’s performance, therefore the driver must
also meet the signal quality criteria in the next section. For example, a rising linear ramp of at 0.8V/ns will generally
produce worse signal quality (more ringback) than an edge that rolls off as it approaches V
TT even though it might have
exceeded that rate earlier. Hi-to-Lo edge rates may exceed this specification and produce acceptable results with a
corresponding reduction in V
OL
. For instance, a buffer with a falling edge rate larger than 1.5V/ns can been deemed
acceptable because it produced a V
OL
less than 500 mV. Lo-to-Hi edges must meet both signal quality and maximum
edge rate specifications.
3. The minimum edge rate is a design target, and slower edge rates can be acceptable, although there is a timing impact
associated with them in the form of an increase in flight time, since the signal at the receiver will no longer meet the
required conditions for T
SU.
Refer to Section 4.1.4 on computing flight time for more details on the effects of edge rates
slower than 0.3 V/ns.
4. These values are not specific to this specification, they are dependent on the location of the driver along a network and
the system requirements such as the number of agents, the distances between agents, the construction of the PCB (Z
0
,
ε
r
, trace width, trace type, connectors), the sockets being used, if any, and the value of the termination resistors. Good
targets for components to be used in an 8-load 66.6 MHz system would be: T
CO_MAX
= 4.5 ns, T
CO_MIN
= 1 ns, T
SU
=
2.5 ns, and T
HD
= 0.
5. This value is specified at the output pin of the device. T
CO
should be measured at the test probe point shown in the
Figure 32, but the delay caused by the 50Ω transmission line must be subtracted from the measurement to achieve an
accurate value for T
co
at the output pin of the device. For simulation purposes, the tester load can be represented as a
single 25Ω termination resistor connected directly to the pin of the device.
6. See Section 4.2.3 for a description of the procedure for determining the receiver’s minimum required setup and hold
times.
4.2.2.1. Output Driver Acceptance Criteria
Although Section 4.1.4 describes ways of amending
flight time to a receiver when the edge rate is lower
than the requirements shown in Table 22, or when
there is excessive ringing, it is still preferable to avoid
slow edge rates or excessive ringing through good
driver and system design, hence the criteria
presented in this section.
As mentioned in note 2 of the previous section, the
criteria for acceptance of an output driver relate to
the edge rate and the signal quality for the Lo-to-Hi
transition, and primarily to the signal quality for the
Hi-to-Lo transition when the device, with its targeted
package, is simulated into the Ref8n network
(Figure 36). The edge rate portion of the AC
specification is a good initial target, but is insufficient
for guaranteeing acceptable performance.