Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
4
1.0. INTRODUCTION
The Pentium Pro processor is the next in the
Intel386™, Intel486™, and Pentium family of proc-
essors. The Pentium Pro processor implements a
Dynamic Execution microarchitecture—a unique
combination of multiple branch prediction, data flow
analysis, and speculative execution.
The Pentium Pro processor is upgradable by a
future OverDrive
®
processor and matching voltage
regulator module described in Section 8.
Increasing clock frequencies and silicon density can
complicate system designs. The Pentium Pro
processor integrates several system components
which alleviate some of the previous system
burdens. The second level cache, cache controller,
and the Advanced Programmable Interrupt
Controller (APIC) are some of the components that
existed in previous Intel processor family systems
which are integrated into this single component.
This integration results in the Pentium Pro
processor bus more closely resembling a symmetric
multiprocessing (SMP) system bus rather than
resembling a previous generation processor-to-
cache bus. This added level of integration and
improved performance, results in higher power
consumption and a new bus technology. This
means it is more important than ever to ensure
adherence to this specification.
A significant new feature of the Pentium Pro
processor, from a system perspective, is the built-in
direct multiprocessing support. In order to achieve
multi-processing for up to four processors, and
maintain the memory and Input/Output (I/O)
bandwidth to support them, new system designs are
needed. In creating a system with multiple
processors, it is important to consider the additional
power burdens and signal integrity issues of
supporting up to 8 loads on a high-speed bus.
1.1. Terminology
A ‘#’ symbol after a signal name refers to an active
low signal. This means that a signal is in the active
state (based on the name of the signal) when driven
low. For example, when FLUSH# is low a flush has
been requested. When Nonmaskable Interrupt
(NMI) is high, a Non-maskable interrupt has
occurred. In the case of lines where the name does
not imply an active state but describes part of a
binary sequence (such as address or data), the ‘#’
symbol implies that the signal is inverted. For
example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D#[3:0] = ‘LHLH’ also refers to a hex ‘A’. (H= High
logic level, L= Low logic level)
The word
Preliminary appears occasionally. Check
with your local Field Applications Engineer for
recent information.
1.2. References
The following are referenced within this
specification:
•
Pentium
®
Pro Processor I/O Buffer Models —
IBIS Format (On world wide web page
http://www.intel.com)
• AP-523,
Pentium
®
Pro Processor Power
Distribution Guidelines
Application Note (Order
Number 242764)
• AP-524,
Pentium
®
Pro Processor GTL+
Layout Guidelines
Application Note (Order
Number 242765)
• AP-525,
Pentium
®
Pro Processor Thermal
Design Guidelines
Application Note (Order
Number 242766)
•
Pentium
®
Pro Processor Developer’s Manual,
Volume 1: Specifications
(Order Number
242690)
•
Pentium
®
Pro Processor Developer’s Manual,
Volume 2: Programmer’s Reference Manual
(Order Number 242691)
•
Pentium
®
Pro Processor Developer’s Manual,
Volume 3: Operating System Writer’s Guide
(Order Number 242692)
2.0. PENTIUM
®
PRO PROCESSOR
ARCHITECTURE OVERVIEW
The Pentium Pro processor has a decoupled, 12-
stage, superpipelined implementation, trading less
work per pipestage for more stages. The Pentium
Pro processor also has a pipestage time 33 percent
less than the Pentium processor, which helps
achieve a higher clock rate on any given process.
The approach used by the Pentium Pro processor
removes the constraint of linear instruction
sequencing between the traditional “fetch” and