Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
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4.1.1. System DC Parameters
The following system DC parameters apply to Figure 22.
Table 18. System DC Parameters
Symbol Parameter Value Tolerance Notes
V
TT
Termination Voltage 1.5 V ±10%
V
REF
Input Reference Voltage 2/3 V
TT
±2% 1
R
T
Termination Resistance Z
EFF
(nominal) See Note 2, 4
Z
EFF
Effective (Loaded) Network Impedance 45–65 Ω 2, 3
NOTES:
1. This ±2% tolerance is in addition to the ±10% tolerance of V
TT
, and could be caused by such factors as voltage divider
inaccuracy.
2.
Zo (nominal)
Z
EFF
= 
(1+Cd/Co)
1/2
3. Zo = Nominal board impedance; recommended to be 65Ω ±10%. Zo is a function of the trace cross-section, the distance
to the reference plane(s), the dielectric constant, ε
r
, of the PCB material and the dielectric constant of the solder-mask/air
for micro-strip traces.
Co = Total intrinsic nominal trace capacitance between the first and last bus agents, excluding the termination resistor
tails. Co is a function of Zo and εr. For Zo= 65 Ω and ε
r
= 4.3, Co is approximately 2.66 pF/in times the network length
(first agent to last agent).
Cd = Sum of the Capacitance of all devices and PCB stubs (if any) attached to the net,
= PCB Stub Capacitance +Socket Capacitance +Package Stub Capacitance + Die Capacitance.
4. Z
EFF
of all 8-load nets must remain between 45-65 Ω under all conditions, including variations in Zo, Cd, temperature,
V
CC
, etc.
5. To reduce cost, a system would usually employ one value of R
T
for all its GTL+ nets, irrespective of the Z
EFF
of individual
nets. The designer may start with the average value of Z
EFF
in the system. The value of R
T
may be adjusted to balance
the Hi-to-Lo and Lo-to-Hi noise margins. Increasing the value of R
T
tends to slow the rising edge, increasing rising flight
time, decreasing the Lo-to-Hi noise margin, and increasing the Hi-to-Lo noise margin by lowering V
OL
. R
T
can be
decreased for the opposite effects.
R
T
affects GTL+ rising edge rates and the “apparent clock-to-out” time of a driver in a net as follows: A large R
T
causes
the standing current in the net to be low when the (open drain) driver is low (on). As the driver switches off, the small
current is turned off, launching a relatively small positive-going wave down the net. After a few trips back and forth
between the driver and the terminations (undergoing reflections at intervening agents in the meantime) the net voltage
finally climbs to V
TT
. Because the wave launched initially is relatively small in amplitude (than it would have been had R
T
been smaller and the standing current larger), the overall rising edge climbs toward V
TT
at a slower rate. Notice that this
effect causes an increase in flight time, and has no influence on the true clock-to-out timing of the driver into the standard
25 Ω test load.
4.1.2. Topological Guidelines
The board routing should use layout design rules
consistent with high-speed digital design (i.e.,
minimize trace length and number of vias, minimize
trace-to-trace coupling, maintain consistent
impedance over the length of a net, maintain
consistent impedance from one net to another,
ensure sufficient power to ground plane bypassing,
etc.). In addition, the signal routing should be done in
a Daisy Chain topology (such as shown in Figure 7)
without any significant stubs. Table 19 describes,
more completely, some of these guidelines. Note that
the critical distances are measured in electrical
length (propagation time) instead of physical length.