Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
30
Table 16. Boundary Scan Interface AC Specifications
T# Parameter Min Max Unit Figure
Notes
T30: TCK Frequency — 16 MHz
T31: TCK Period 62.5 — ns Figure 13
T32: TCK High Time 25 ns Figure 13
@2.0 V, 1
T33: TCK Low Time 25 ns Figure 13
@0.8 V, 1
T34: TCK Rise Time 5 ns Figure 13
(0.8 V-2.0 V), 1,
2
T35: TCK Fall Time 5 ns Figure 13
(2.0 V-0.8 V), 1,
2
T36: TRST# Pulse Width 40 ns Figure 21
1, Asynchronous
T37: TDI, TMS Setup Time 5 ns Figure 20
3
T38: TDI, TMS Hold Time 14 ns Figure 20
3
T39: TDO Valid Delay 1 10 ns Figure 20
4, 5
T40: TDO Float Delay 25 ns Figure 20
1, 4, 5
T41: All Non-Test Outputs
Valid Delay
2 25 ns Figure 20
4, 6, 7
T42: All Non-Test Outputs
Float Delay
25 ns Figure 20
1, 4, 6, 7
T43: All Non-Test Inputs
Setup Time
5 ns Figure 20
3, 6, 7
T44: All Non-Test Inputs
Hold Time
13 ns Figure 20
3, 6, 7
NOTES:
1. Not 100% tested. Guaranteed by design/characterization.
2. 1ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.
3. Referenced to TCK rising edge.
4. Referenced to TCK falling edge.
5. Valid delay timing for this signal is specified into 150 Ω terminated to 3.3 V.
6. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO and TMS). These
timings correspond to the response of these signals due to boundary scan operations. PWRGOOD should be driven high
throughout boundary scan testing.
7. During Debug Port operation, use the normal specified timings rather than the boundary scan timings.