Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz

Table 15. APIC Clock and APIC I/O AC Specifications

T# Parameter Min Max Unit Figure Notes

T21A: PICCLK Frequency 2 33.3 MHz

T21B: FRC Mode BCLK to

PICCLK offset

1 5 ns Figure 16 1

T22: PICCLK Period 30 500 ns Figure 13

T23: PICCLK High Time 12 ns Figure 13

T24: PICCLK Low Time 12 ns Figure 13

T25: PICCLK Rise Time 1 5 ns Figure 13

T26: PICCLK Fall Time 1 5 ns Figure 13

T27: PICD[1:0] Setup Time 8 ns Figure 15 2

T28: PICD[1:0] Hold Time 2 ns Figure 15 2

T29: PICD[1:0] Valid Delay 2.1 10 ns Figure 14 2, 3, 4

NOTES:

1. With FRC enabled PICCLK must be ¼X BCLK and synchronized with respect to BCLK. PICCLK must always lag BCLK

by at least 1 ns and no more than 5 ns.

2. Referenced to PICCLK Rising Edge.

3. For open drain signals, Valid Delay is synonymous with Float Delay.

4. Valid delay timings for these signals are specified into 150 Ω to 3.3 V.