Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E

Table 14. Reset Conditions AC Specifications

T# Parameter Min Max Unit Figure Notes

T16: Reset Configuration Signals

(A[14:5]#, BR0#, FLUSH#,

INIT#) Setup Time

4 BCLKs Figure 18 Before deassertion

of RESET#

T17: Reset Configuration Signals

(A[14:5]#, BR0#, FLUSH#,

INIT#) Hold Time

2 20 BCLKs Figure 18 After clock that

deasserts RESET#

T18: Reset Configuration Signals

(A20M#, IGNNE#,

LINT[1:0]#) Setup Time

1 ms Figure 18 Before deassertion

of RESET#

T19: Reset Configuration Signals

(A20M#, IGNNE#,

LINT[1:0]#) Delay Time

5 BCLKs Figure 18 After assertion of

RESET#

T20: Reset Configuration Signals

(A20M#, IGNNE#,

LINT[1:0]#) Hold Time

2 20 BCLKs Figure 18

Figure 19

After clock that

deasserts RESET#

NOTES:

1. For a reset, the clock ratio defined by these signals must be a safe value (their final or lower multiplier) within this delay

unless PWRGOOD is being driven inactive.