Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
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Table 13. 3.3 V Tolerant Signal Groups AC Specifications
T# Parameter Min Max Unit Figure Notes
T11: 3.3 V Tolerant Output Valid Delay 1 8 ns Figure 14 1
T12: 3.3 V Tolerant Input Setup Time 5 ns Figure 15 2, 3, 4, 5
T13: 3.3 V Tolerant Input Hold Time 1.5 ns Figure 15
T14: 3.3 V Tolerant Input Pulse Width,
except PWRGOOD
2 BCLKs Figure 14 Both levels
T15: PWRGOOD Inactive Pulse Width 10 BCLKs Figure 14
Figure 19
6
NOTES:
1. Valid delay timings for these signals are specified into 150 Ω to 3.3 V. See Figure 13 for a capacitive derating curve.
2. These inputs may be driven asynchronously. However, to guarantee recognition on a specific clock, the setup and hold
times with respect to BCLK must be met.
3. These signals must be driven synchronously in FRC mode.
4. A20M#, IGNNE#, INIT# and FLUSH# can be asynchronous inputs, but to guarantee recognition of these signals following
a synchronizing instruction such as an I/O write instruction, they must be valid with active RS[2:0]# signals of the
corresponding synchronizing bus transaction.
5. INTR and NMI are only valid in APIC disable mode. LINT[1:0]# are only valid in APIC enabled mode.
6. When driven inactive, or after Power, V
REF
, BCLK, and the ratio signals are stable.
7.00
7.50
8.00
8.50
9.00
9.50
10.00
10.50
11.00
11.50
12.00
0 5 10 15 20 25 30 35 40 45 50
pF
ns
Figure 12. 3.3 V Tolerant Group Derating Curve