Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
26
Table 11. GTL+ Signal Groups AC Specifications
T# Parameter Min Max Unit Figure Notes
T7A: GTL+ Output Valid Delay
H→L
0.55
0.80
4.4
4.4
ns
ns
Figure 14 @ 150 MHz, 256K L2
All other components
1, 2
T7B: GTL+ Output Valid Delay
L→H
0.55
0.80
3.9
3.9
ns
ns
Figure 14 @ 150 MHz, 256K L2
All other components
1, 2
T8: GTL+ Input Setup Time 2.2 ns Figure 15 3, 4, 5
T9: GTL+ Input Hold Time 0.45
0.70
ns
ns
Figure 15 @ 150 MHz, 256K L2
All other components
5
T10: RESET# Pulse Width 1 ms Figure 18
Figure 19
6
NOTES:
1. Valid delay timings for these signals are specified into an idealized 25 Ω resistor to 1.5 V with V
REF
at 1.0V. Minimum
values guaranteed by design. See Figure 32 for the actual test configuration.
2. GTL+ timing specifications for 166MHz and higher components are PRELIMINARY. Consult you local FAE.
3. A minimum of 3 clocks must be guaranteed between 2 active-to-inactive transitions of TRDY#.
4. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
5. Specification takes into account a 0.3 V/ns edge rate and the allowable V
REF
variation. Guaranteed by design.
6. After V
CC
, V
TT
, V
REF
, BCLK and the clock ratio become stable.
Table 12. GTL+ Signal Groups Ringback Tolerance
Parameter Min
Unit
Figure
Notes
α: Overshoot 100
mV
Figure 17
1
τ: Minimum Time at High 1.5
ns
Figure 17
1
ρ: Amplitude of Ringback -100
mV
Figure 17
1
δ: Duration of Squarewave Ringback N/A
ns
Figure 17
1
φ: Final Settling Voltage 100
mV
Figure 17
1
NOTES:
1. Specified for an edge rate of 0.3—0.8V/ns. See Section 4.1.3.1 for the definition of these terms. See Figure 24 and
Figure 25 for the generic waveforms. All values determined by design/characterization.