Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
25
Table 9. Bus Clock AC Specifications
T# Parameter Min Max Unit
Figure
Notes
Core Frequency 100
150
150
150
150
166.67
180
200
MHz
MHz
MHz
MHz
@ 150 MHz
@ 166 MHz
@ 180 MHz
@ 200 MHz
1
Bus Frequency 50.00 66.67 MHz All Frequencies, 1
T1: BCLK Period 15 20 ns
Figure 13
All Frequencies
T2: BCLK Period Stability 300 ps 2, 3
T3: BCLK High Time 4 ns
Figure 13
@>2.0 V, 2
T4: BCLK Low Time 4 ns
Figure 13
@<0.8 V, 2
T5: BCLK Rise Time 0.3 1.5 ns
Figure 13
(0.8 V - 2.0 V), 2
T6: BCLK Fall Time 0.3 1.5 ns
Figure 13
(2.0 V- 0.8 V),2
NOTES:
1. The internal core clock frequency is derived from the bus clock. A clock ratio must be driven into the Pentium
®
Pro
processor on the signals LINT[1:0], A20M# and IGNNE# at reset. See the descriptions for these signals in Appendix A.
2. Not 100% tested. Guaranteed by design/characterization.
3. Measured on rising edge of adjacent BCLKs at 1.5 V.
The jitter present must be accounted for as a component of BCLK skew between devices.
Clock jitter is measured from one rising edge of the clock signal to the next rising edge at 1.5V. To remain within the clock
jitter specifications, all clock periods must be within 300 ps of the ideal clock period for a given frequency. For example, a
66.67 MHz clock with a nominal period of 15 ns, must not have any single clock period that is greater than 15.3 ns or less
than 14.7 ns.
Table 10. Supported Clock Ratios
1
Component: 2X 5/2X 3X 7/2X 4X
150 MHz XXX
166 MHz XX
180 MHz XX
200 MHz XX X
NOTES:
1. Only those indicated by an ‘X’ are tested during the manufacturing test process.