Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
18
both processors. Also note the timing requirements
for PICCLK with respect to BCLK. With FRC
enabled, PICCLK must be ¼X BCLK and
synchronized with respect to BCLK. PICCLK must
always lag BCLK by at least 1 ns and no more than
5 ns.
Table 2. Signal Groups
Group Name Signals
GTL+ Input BPRI#, BR[3:1]#
1
, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
GTL+ Output PRDY#
GTL+ I/O A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,
BPM[1:0]#, BR0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, FRCERR, HIT#,
HITM#, LOCK#, REQ[4:0]#, RP#
3.3 V Tolerant Input A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#,
PWRGOOD
2
, SMI#, STPCLK#
3.3 V Tolerant Output FERR#, IERR#, THERMTRIP#
3
Clock
4
BCLK
APIC Clock
4
PICCLK
APIC I/O
4
PICD[1:0]
JTAG Input
4
TCK, TDI, TMS, TRST#
JTAG Output
4
TDO
Power/Other
5
CPUPRES#, PLL1, PLL2, TESTHI, TESTLO, UP#, V
CC
P, V
CC
S, V
CC
5,
VID[3:0], V
REF
[7:0], V
SS
NOTES:
1. The BR0# pin is the only BREQ# signal that is bi-directional. The internal BREQ# signals are mapped onto BR# pins after
the agent ID is determined.
2. See PWRGOOD in Section 3.9.
3. See THERMTRIP# in Section 3.10.
4. These signals are tolerant to 3.3V. Use a 150Ω pull-up resistor on PICD[1:0] and 240Ω on TDO.
5. CPUPRES# is a ground pin defined to allow a designer to detect the presence of a processor in a socket. (preliminary)
PLL1 and PLL2 are for decoupling the internal PLL (See Section 3.4.3.).
TESTHI pins should be tied to VCCP. A 10K pull-up may be used. See Section 3.11.
TESTLO pins should be tied to V
SS
. A 1K pull-down may be used. See Section 3.11.
UP# is an open in the Pentium
®
Pro processor and tied to V
SS
in the OverDrive
®
processor (see Section 8.3.2 for usage).
V
CC
P is the primary power supply.
V
CC
S is the secondary power supply used by some versions of the second level cache.
V
CC
5 is unused by Pentium Pro processor and is used by the OverDrive processor for fan/heatsink power. See
Section 8.
VID[3:0] lines are described in Section 3.6.
V
REF
[7:0] are the reference voltage pins for the GTL+ buffers.
V
SS
is ground.