Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
17
Support for a wider range of VID settings will benefit
the system in meeting the power requirements of
future Pentium Pro processors. Note that the ‘1111’
(or all opens) ID can be used to detect the absence
of a processor in a given socket as long as the power
supply used does not affect these lines.
To use these pins, they may need to be pulled up by
an external resistor to another power source. The
power source chosen should be one that is
guaranteed to be stable whenever the supply to the
voltage regulator is stable. This will prevent the
possibility of the Pentium Pro processor supply run-
ning up to 3.5 V in the event of a failure in the supply
for the VID lines. Note that the specification for the
standard Pentium Pro Voltage Regulator Modules
allows the use of these signals either as TTL
compatible levels or as opens and shorts. Using
them as TTL compatible levels will require the use of
pull-up resistors to 5 V if the input voltage to the
regulator is 5 V and the use of a voltage divider if the
input voltage to the regulator is 12 V. The resistors
chosen should not cause the current through a VID
pin to exceed its specification in Table 3. There must
not be any other components on these signals if the
VRM uses them as opens and shorts.
3.7. JTAG Connection
The debug port described in the Pentium® Pro
Processor Developer’s Manual, Volume 1:
Specifications
(Order Number 242690) should be at
the start and end of the JTAG chain with TDI to the
first component coming from the Debug Port and
TDO from the last component going to the Debug
Port. The recommended pull-up value for Pentium
Pro processor TDO pins is 240Ω.
Due to the voltage levels supported by the Pentium
Pro processor JTAG logic, it is recommended that
the Pentium Pro processors and any other 3.3 V
logic level components within the system be first in
the JTAG chain. A translation buffer should be used
to connect to the rest of the chain unless a 5 V com-
ponent can be used next that is capable of accepting
a 3.3 V input. Similar considerations must be made
for TCK, TMS and TRST#. Components may need
these signals buffered to match required logic levels.
In a multiprocessor system, be cautious when
including empty Pentium Pro processor sockets in
the scan chain. All sockets in the scan chain must
have a processor installed to complete the chain or
the system must support a method to bypass the
empty sockets.
See the
Pentium® Pro Processor Developer’s
Manual, Volume 1: Specifications
(Order Number
242690) for full information on putting a debug port in
the JTAG chain.
3.8. Signal Groups
In order to simplify the following discussion, signals
have been combined into groups by buffer type. All
outputs are open drain and require an external
high-level source provided externally by the
termination or a pull-up resistor.
GTL+ input signals have differential input buffers
which use V
REF
as their reference signal. GTL+
output signals require termination to 1.5 V. Later in
this document, the term “GTL+ Input” refers to the
GTL+ input group as well as the GTL+ I/O group
when receiving. Similarly, “GTL+ Output” refers to
the GTL+ output group as well as the GTL+ I/O
group when driving.
The 3.3 V tolerant, Clock, APIC and JTAG inputs can
each be driven from ground to 3.3V. The 3.3 V
tolerant, APIC, and JTAG outputs can each be pulled
high to as much as 3.3 V. See Table 7 for
specifications.
The groups and the signals contained within each
group are shown in Table 2. Note that the signals
ASZ[1:0]#, ATTR[7:0]#, BE[7:0]#, BREQ#[3:0],
DEN#, DID[7:0]#, DSZ[1:0]#, EXF[4:0]#, LEN[1:0]#,
SMMEM#, and SPLCK# are all GTL+ signals that are
shared onto another pin. Therefore they do not
appear in this table.
3.8.1. ASYNCHRONOUS VS.
SYNCHRONOUS
All GTL+ signals are synchronous. All of the 3.3 V
tolerant signals can be applied asynchronously,
except when running two processors in FRC mode.
To run in FRC mode, synchronization logic is
required on all signals, (except PWRGOOD) going to