Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
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3.4.3. PHASE LOCK LOOP (PLL)
DECOUPLING
Isolated analog decoupling is required for the internal
PLL. This should be equivalent to 0.1µF of ceramic
capacitance. The capacitor should be type Y5R or
better and should be across the PLL1 and PLL2 pins
of the Pentium Pro processor. (“Y5R” implies ±15%
tolerance over the temperature range -30°C to
+85°C.)
3.5. BCLK Clock Input Guidelines
The BCLK input directly controls the operating speed
of the GTL+ bus interface. All GTL+ external timing
parameters are specified with respect to the rising
edge of the BCLK input. Clock multiplying within the
processor is provided by an internal Phase Lock
Loop (PLL) which requires a constant frequency
BCLK input. Therefore the BCLK frequency cannot
be changed dynamically. It can however be changed
when RESET# is active assuming that all reset
specifications are met for the clock and the
configuration signals.
The Pentium Pro processor core frequency must be
configured during reset by using the A20M#,
IGNNE#, LINT1/NMI, and LINT0/INTR pins. The
value on these pins during RESET#, and until two
clocks beyond the end of the RESET# pulse,
determines the multiplier that the PLL will use for the
internal core clock. See the Appendix A for the
definition of these pins during reset. At all other times
their functionality is defined as the compatibility
signals that the pins are named after. These signals
are 3.3 V tolerant and may be driven by existing logic
devices. This is important for both functions of the
pins.
Supplying a bus clock multiplier this way is required
in order to increase processor performance without
changing the processor design, and to maintain the
bus frequency such that system boards can be
designed to function properly as CPU frequencies
increase.
3.5.1. SETTING THE CORE CLOCK TO BUS
CLOCK RATIO
Table 44 lists the configuration pins and the values
that must be driven at reset time in order to set the
core clock to bus clock ratio. Figure 9 shows the
timing relationship required for the clock ratio signals
with respect to RESET# and BCLK. CRESET# from
an 82453GX (or 82453KX) is shown since its timing
is useful for controlling the multiplexing function that
is required for sharing the pins.