Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
114
• If the transaction also has a request initiated
transfer, that the request initiated TRDY# was
asserted and then deasserted (TRDY# must be
deasserted for at least one clock between the
TRDY# for the write and the TRDY# for the
implicit writeback),
• A minimum of 1 clock after RS[2:0]# active
assertion for transaction “n-1”. After the
transaction reaches the top of the In-order
Queue).
TRDY# for a write or an implicit writeback may be
deasserted when:
• Inactive DBSY# and active TRDY# are
observed.
• DBSY# is observed inactive on the clock
TRDY# is asserted.
• A minimum of three clocks can be guaranteed
between two active-to-inactive transitions of
TRDY#
• The response is driven on RS[2:0]#.
• Inactive DBSY# and active TRDY# are
observed for a write, and TRDY# is required for
an implicit writeback.
A.56 TRST (I)
The TRST# signal resets the JTAG logic.