Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
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of the Request Phase on the EXF4#/Ab7# signal. It is
asserted by the Pentium Pro processor to indicate
that the processor is in System Management Mode
and is executing out of SMRAM space.
A.49 SPLCK# (I/O)
The SPLCK# signal is the Split Lock signal. It is
driven in the second clock of the Request Phase on
the EXF3#/Ab6# signal of the first transaction of a
locked operation. It is driven to indicate that the
locked operation will consist of four locked
transactions. Note that SPLCK# is asserted only for
locked operations and only in the first transaction of
the locked operation.
A.50 STPCLK# (I)
The STPCLK# signal is the Stop Clock signal. When
asserted, the Pentium Pro processor enters a low-
power state, the stop-clock state. The processor
issues a Stop Clock Acknowledge special
transaction, and stops providing internal clock
signals to all units except the bus unit and the APIC
unit. The processor continues to snoop bus
transactions and service interrupts while in stop
clock state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has
no effect on the bus clock.
STPCLK# is an asynchronous input. In FRC mode,
STPCLK# must be synchronous to BCLK.
A.51 TCK (I)
The TCK signal is the System Support group Test
Clock signal. TCK provides the clock input for the
test bus (also known as the test access port). Make
certain that TCK is active before initializing the TAP.
A.52 TDI(I)
The TDI signal is the System Support group test-
data-in signal. TDI transfers serial test data into the
Pentium Pro processor. TDI provides the serial input
needed for JTAG support.
A.53 TDO (O)
The TDO signal is the System Support group test-
data-out signal. TDO transfers serial test data out
from the Pentium Pro processor. TDO provides the
serial output needed for JTAG support.
A.54 TMS (I)
The TMS signal is an additional System Support
group JTAG-support signal.
A.55 TRDY (I)
The TRDY# signal is the target Ready signal. It is
asserted by the target in the Response Phase to
indicate that the target is ready to receive write or
implicit writeback data transfer. This enables the
request initiator or the snooping agent to begin the
appropriate data transfer. There will be no data
transfer after a TRDY# assertion if a write has zero
length indicated in the Request Phase. The data
transfer is optional if an implicit writeback occurs for
a transaction which writes a full cache line (the
Pentium Pro processor will perform the implicit
writeback).
TRDY# for a write transaction is driven by the
addressed agent when:
• When the transaction has a write or writeback
data transfer
• It has a free buffer available to receive the write
data
• A minimum of 3 clocks after ADS# for the
transaction
• The transaction reaches the top-of-the-In-order
Queue
• A minimum of 1 clock after RS[2:0]# active
assertion for transaction “n-1”. (After the
transaction reaches the top of the In-order
Queue).
TRDY# for an implicit writeback is driven by the
addressed agent when:
• The transaction has an implicit writeback data
transfer indicated in the Snoop Result Phase.
• It has a free cache line buffer to receive the
cache line writeback