Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
112
Table 54. Transaction Response Encodings
RS[2:0] Description
HITM#
DEFER#
000 Idle State.
N/A
N/A
001 Retry Response. The transaction is canceled and must be retried
by the initiator.
0
1
010 Defer Response. The transaction is suspended. The defer agent
will complete it with a defer reply
0
1
011 Reserved.
0
1
100 Hard Failure. The transaction received a hard error. Exception
handling is required.
X
X
101 Normal without data
0
0
110 Implicit WriteBack Response. Snooping agent will transfer the
modified cache line on the data bus.
1
X
111 Normal with data.
0
0
• The response agent must return an Implicit
writeback response in the next clock for a read
transaction with HITM# asserted in the Snoop
Phase, when the addressed agent samples
TRDY# active and DBSY# inactive.
• The addressed agent must return an Implicit
writeback response in the clock after the
following sequence is sampled for a write
transaction with HITM# asserted:
1. TRDY# active and DBSY# inactive
2. Followed by TRDY# inactive
3. Followed by TRDY# active and DBSY#
inactive
• The defer agent can return a Deferred, Retry, or
Split response anytime for a read transaction
with HITM# deasserted and DEFER# asserted.
• The defer agent can return Deferred, Retry, or
Split response when it samples TRDY# active
and DBSY# inactive for a write transaction with
HITM# deasserted and DEFER# asserted.
A.46 RSP# (I)
The RSP# signal is the Response Parity signal. It is
driven by the response agent during assertion of
RS[2:0]#. RSP# provides parity protection for
RS[2:0]#.
A correct parity signal is high if an even number of
covered signals are low and low if an odd number of
covered signals are low. During Idle state of RS[2:0]#
(RS[2:0]#=000), RSP# is also high since it is not
driven by any agent guaranteeing correct parity.
Pentium Pro processor bus agents can check RSP#
at all times and if a parity error is observed, treat it as
a protocol violation error. If the BINIT# driver is
enabled during configuration, the agent observing
RSP# parity error can assert BINIT#.
A.47 SMI# (I)
System Management Interrupt is asserted
asynchronously by system logic. On accepting a
System Management Interrupt, the Pentium Pro
processor saves the current state and enters SMM
mode. It issues an SMI Acknowledge Bus transaction
and then begins program execution from the SMM
handler.
A.48 SMMEM# (I/O)
The SMMEM# signal is the System Management
Mode Memory signal. It is driven on the second clock