Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
110
Table 53. Transaction Types Defined by REQa#/REQb# Signals
REQa[4:0]# REQb[4:0]#
Transaction 4 3 2 1
0
43 2 1 0
Deferred Reply 0 0 0 0
0
XX X X X
Rsvd (Ignore) 0 0 0 0
1
XX X X X
Interrupt Acknowledge 0 1 0 0
0
DSZ# X 0 0
Special Transactions 0 1 0 0
0
DSZ# X 0 1
Rsvd (Central agent
response)
0100
0
DSZ# X 1 X
Branch Trace Message 0 1 0 0
1
DSZ# X 0 0
Rsvd (Central agent
response)
0100
1
DSZ# X 0 1
Rsvd (Central agent
response)
0100
1
DSZ# X 1 X
I/O Read 1 0 0 0
0
DSZ# X LEN#
I/O Write 1 0 0 0
1
DSZ# X LEN#
Rsvd (Ignore) 1 1 0 0
X
DSZ# X X X
Memory Read &
Invalidate
ASZ# 0 1
0
DSZ# X LEN#
Rsvd (Memory Write) ASZ# 0 1
1
DSZ# X LEN#
Memory Code Read ASZ# 1 D/C#=0
0
DSZ# X LEN#
Memory Data Read ASZ# 1 D/C#=1
0
DSZ# X LEN#
Memory Write (may not
be retried)
ASZ# 1 W/WB#
=0
1
DSZ# X LEN#
Memory Write (may not
be retried)
ASZ# 1 W/WB#
=1
1
DSZ# X LEN#
A.43 RESET# (I)
The RESET# signal is the Execution Control group
reset signal. Asserting RESET# resets all Pentium
Pro processors to known states and invalidates their
L1 and L2 caches without writing back Modified (M
state) lines. For a power-on type reset, RESET#
must stay active for at least one millisecond after
V
CC
P and CLK have reached their proper DC and
AC specifications. On observing active RESET#, all
bus agents must deassert their outputs within two
clocks.
A number of bus signals are sampled at the active-
to-inactive transition of RESET# for the power-on
configuration. The configuration options are
described in the
Pentium® Pro Processor
Developer’s Manual, Volume 1: Specifications (Order
Number 242690) and in the pertinent signal
descriptions in this appendix.