Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
108
A.33 INIT# (I)
The INIT# signal is the Execution Control group
initialization signal. Active INIT# input resets integer
registers inside all Pentium Pro processors without
affecting their internal (L1 or L2) caches or their
floating-point registers. Each Pentium Pro processor
begins execution at the power-on reset vector
configured during power-on configuration regardless
of whether INIT# has gone inactive. The processor
continues to handle snoop requests during INIT#
assertion.
INIT# can be used to help performance of DOS
extenders written for the Intel 80286 processor. INIT#
provides a method to switch from protected mode to
real mode while maintaining the contents of the
internal caches and floating-point state. INIT# can not
be used in lieu of RESET# after power-up.
On active-to-inactive transition of RESET#, each
Pentium Pro processor bus agent samples INIT#
signals to determine its power-on configuration. Two
clocks after RESET# is sampled deasserted, these
signals begin normal operation.
INIT# is an asynchronous input. In FRC mode, INIT#
must be synchronous to BCLK.
A.34 INTR (I)
The INTR signal is the Interrupt Request signal. The
INTR input indicates that an external interrupt has
been generated. The interrupt is maskable using the
IF bit in the EFLAGS register. If the IF bit is set, the
Pentium Pro processor vectors to the interrupt
handler after the current instruction execution is
completed. Upon recognizing the interrupt request,
the Pentium Pro processor issues a single Interrupt
Acknowledge (INTA) bus transaction. INTR must
remain active until the INTA bus transaction to
guarantee its recognition.
INTR is sampled on every rising BCLK edge. INTR is
an asynchronous input but recognition of INTR is
guaranteed in a specific clock if it is asserted
synchronously and meets the setup and hold times.
INTR must also be deasserted for a minimum of two
clocks to guarantee its inactive recognition. In FRC
mode, INTR must be synchronous to BCLK. On
power-up the LINT[1:0] signals are used for power-
on-configuration of clock ratios. Both these signals
must be software configured by programming the
APIC register space to be used either as NMI/INTR
or LINT[1:0] in the BIOS. Because APIC is enabled
after reset, LINT[1:0] is the default configuration.
A.35 LEN[1:0]# (I/O)
The LEN[1:0]# signals are data-length signals. They
are transmitted using REQb[1:0]# signals by the
request initiator in the second clock of Request
Phase. LEN[1:0]# define the length of the data
transfer requested by the request initiator as defined
in Table 52. The LEN[1:0]#, HITM#, and RS[2:0]#
signals together define the length of the actual data
transfer.
Table 52. LEN[1:0]# Data Transfer Lengths
LEN[1:0]#
Request Initiator’s Data
Transfer Length
00
0-8 Bytes
01
16 Bytes
10
32 Bytes
11
Reserved
A.36 LINT[1:0] (I)
The LINT[1:0] signals are the Execution Control
group Local Interrupt signals. When APIC is
disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1
becomes NMI, a non-maskable interrupt. INTR and
NMI are backward compatible with the same signals
for the Pentium processor. Both signals are
asynchronous inputs. In FRC mode, LINT[1:0] must
be synchronous to BCLK.
During active RESET#, the Pentium Pro processor
continuously samples the A20M#, IGNNE# and
LINT[1:0] values to determine the ratio of core-clock
frequency to bus-clock frequency. See Table 44.
After the PLL-lock time, the core clock becomes
stable and is locked to the external bus clock. On the
active-to-inactive transition of RESET#, the Pentium
Pro processor latches the ratio internally.
Both these signals must be software configured by
programming the APIC register space to be used
either as NMI/INTR or LINT[1:0] in the BIOS.
Because APIC is enabled after reset, LINT[1:0] is the
default configuration.