Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
107
completes, the Pentium Pro processor de-asserts
FRCERR if BIST completed successfully and
continues to assert FRCERR if BIST fails. If the
Pentium Pro processor does not execute the BIST
action, then it keeps FRCERR asserted for
approximately 20 clocks and then de-asserts it.
The Pentium® Pro Processor Developer’s Manual,
Volume 1: Specifications
(Order Number 242690)
describes how a Pentium Pro processor can be
configured as a master or a checker.
A.30 HIT# (I/O), HITM# (I/O)
The HIT# and HITM# signals are Snoop-hit and Hit-
modified signals. They are snoop results asserted by
any Pentium Pro processor bus agent in the Snoop
Phase.
Any bus agent can assert both HIT# and HITM#
together for one clock in the Snoop Phase to indicate
that it requires a snoop stall. When a stall condition is
sampled, all bus agents extend the Snoop Phase by
two clocks. The stall can be continued by reasserting
HIT# and HITM# together every other clock for one
clock.
A caching agent must assert HITM# for one clock in
the Snoop Phase if the transaction hits a Modified
line, and the snooping agent must perform an implicit
writeback to update main memory. The snooping
agent with the Modified line makes a transition to
Shared state if the original transaction is Read Line
or Read Partial, otherwise it transitions to Invalid
state. A Deferred Reply transaction may have HITM#
asserted to indicate the return of unexpected data.
A snooping agent must assert HIT# for one clock
during the Snoop Phase if the line does not hit a
Modified line in its writeback cache and if at the end
of the transaction it plans to keep the line in Shared
state. Multiple caching agents can assert HIT# in the
same Snoop Phase. If the requesting agent observes
HIT# active during the Snoop Phase it can not cache
the line in Exclusive or Modified state.
On observing a snoop stall, the agents asserting
HIT# and HITM# independently reassert the signal
after one inactive clock so that the correct snoop
result is available, in case the Snoop Phase
terminates after the two clock extension.
A.31 IERR# (O)
The IERR# signal is the Error group Internal Error
signal. A Pentium Pro processor asserts IERR#
when it observes an internal error. It keeps IERR#
asserted until it is turned off as part of the Machine
Check Error or the NMI handler in software, or with
RESET#, BINIT#, and INIT# assertion.
An internal error can be handled in several ways
inside the processor based on its power-on
configuration. If Machine Check Exception (MCE) is
enabled, IERR# causes an MCE entry. IERR# can
also be directed on the BERR# pin to indicate an
error. Usually BERR# is sampled back by all
processors to enter MCE or it can be redirected as
an NMI by the central agent.
A.32 IGNNE# (I)
The IGNNE# signal is the Intel Architecture
Compatability group Ignore Numeric Error signal. If
IGNNE# is asserted, the Pentium Pro processor
ignores a numeric error and continues to execute
non-control floating-point instructions. If IGNNE# is
deasserted, the Pentium Pro processor freezes on a
non-control floating-point instruction if a previous
instruction caused an error.
IGNNE# has no effect when the NE bit in control
register 0 is set.
IGNNE# is an asynchronous input. However, to
guarantee recognition of this signal following an I/O
write instruction, IGNNE# must be valid along with
RS[2:0]# in the Response Phase of the
corresponding I/O Write bus transaction. In FRC
mode, IGNNE# must be synchronous to BCLK.
During active RESET#, the Pentium Pro processor
begins sampling the A20M#, IGNNE# and LINT[1:0]
values to determine the ratio of core-clock frequency
to bus-clock frequency. See Table 44. After the PLL-
lock time, the core clock becomes stable and is
locked to the external bus clock. On the active-to-
inactive transition of RESET#, the Pentium Pro
processor latches A20M# and IGNNE# and freezes
the frequency ratio internally. Normal operation on
the two signals continues two clocks after RESET#
inactive is sampled.